Senior Physical Design Engineer for SoC & FPGA

Altera Corporation; San Jose (CA); On-site; USD 133,000 - 193,000; Full time

Job summary

Altera Corporation is seeking a Physical Design Engineer in San Jose, CA to implement advanced IP and SoC designs, driving timing closure, power optimization, and signoff for next-generation FPGA products.

You will collaborate with RTL, DFT, CAD, architecture, verification, and product engineering teams to deliver manufacturing-ready silicon, with emphasis on performance, reliability, and efficiency. Strong analytical and scripting skills are required for flow automation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline; 5+ years of semiconductor physical design experience.

Responsibilities

• Perform full-chip and block-level physical design implementation from RTL through GDSII.
• Execute synthesis, floorplanning, place and route, CTS, timing closure, and physical optimization.

Skills

Physical design

Timing closure

Debugging

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Tcl scripting

Python scripting

Perl scripting

Shell scripting

Job description

Altera Corporation is seeking a Physical Design Engineer in San Jose, CA to implement advanced IP and SoC designs, driving timing closure, power optimization, and signoff for next-generation FPGA products.

You will collaborate with RTL, DFT, CAD, architecture, verification, and product engineering teams to deliver manufacturing-ready silicon, with emphasis on performance, reliability, and efficiency. Strong analytical and scripting skills are required for flow automation.