Physical Design Engineer (PnR) - ASIC Signoff Expert

Avicena Tech; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Avicena is seeking a Physical Design Engineer (PnR) in Sunnyvale, CA to implement and close digital blocks and top-level partitions of a mixed-signal ASIC. You will work with the PnR lead to take designs from netlist to clean signoff.

Ideal candidates have hands-on experience with Cadence Innovus or Synopsys ICC2/Fusion Compiler, and STA tools such as Tempus or PrimeTime, plus physical verification with Calibre or Pegasus on FinFET flows.

Qualifications

• BS or MS in Electrical or Computer Engineering with 3+ years of ASIC physical design.
• Hands-on experience with Cadence Innovus or Synopsys ICC2/Fusion Compiler, and STA with Tempus or PrimeTime.
• Physical verification with Calibre or Pegasus.
• FinFET implementation experience.
• Tcl and Python scripting.

Responsibilities

• Run synthesis, floorplanning, placement, clock tree synthesis and routing for blocks and partitions.
• Close timing across modes and corners, and implement ECOs.
• Run signoff checks: STA, IR drop and EM, physical verification and logical equivalence.
• Integrate analog macros and repeated arrays following the macro handoff checklist.
• Maintain and improve implementation scripts.
• Support tapeout and post-tapeout ECOs.

Skills

Detail-oriented

Learner

Collaboration

Ownership

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys ICC2

Fusion Compiler

Tempus

PrimeTime

Calibre

Pegasus

Tcl scripting

Python scripting

Job description

Avicena is seeking a Physical Design Engineer (PnR) in Sunnyvale, CA to implement and close digital blocks and top-level partitions of a mixed-signal ASIC. You will work with the PnR lead to take designs from netlist to clean signoff.

Ideal candidates have hands-on experience with Cadence Innovus or Synopsys ICC2/Fusion Compiler, and STA tools such as Tempus or PrimeTime, plus physical verification with Calibre or Pegasus on FinFET flows.