Physical Design Signoff Engineer

Mirafra Technologies; Mountain View (CA); On-site; USD 160,000 - 210,000; Full time

Job summary

Mirafra Technologies is seeking an experienced Physical Design Signoff Engineer to drive timing, signoff closure, and power integrity for advanced-node ASIC/SoC designs. The role requires hands-on work with Fusion Compiler, PrimeTime, RedHawk, and Calibre to ensure robust tapeout readiness.

You will coordinate with PD, STA, synthesis, RTL, library and foundry teams to resolve signoff issues and validate methodologies, constraints, and ECO implementations across full-chip and block-level signoff.

Qualifications

Responsibilities

• Own physical design signoff and closure from post-route through tapeout.
• Perform STA signoff using Synopsys PrimeTime across multiple PVT corners and modes.
• Analyze and resolve setup/hold violations, max transition, capacitance issues, clock skew and latency, timing exceptions and unconstrained paths, SI/crosstalk violations.
• Work with PD team using Fusion Compiler to drive timing, congestion and physical closure.
• Perform IR-drop and EM analysis using Ansys Apache RedHawk and analyze power distribution and EM violations.

Job description

We are looking for an experienced Physical Design Signoff Engineer with strong expertise in timing, physical verification, power integrity, and signoff closure for advanced-node ASIC/SoC designs. The ideal candidate should have hands-on experience with Synopsys Fusion Compiler, PrimeTime, Ansys Apache RedHawk, and Siemens Calibre, preferably on 5nm or more advanced process technologies.

Key Responsibilities

• Own physical design signoff and closure from post-route through tapeout.
• Perform STA signoff using Synopsys PrimeTime across multiple PVT corners and modes.
• Analyze and resolve:
  • Setup and hold violations
  • Max transition and capacitance violations
  • Clock skew and latency issues
  • Timing exceptions and unconstrained paths
  • SI/crosstalk-induced timing violations
• Work closely with the physical implementation team using Synopsys Fusion Compiler to drive timing, congestion, and physical closure.
• Perform IR-drop and electromigration (EM) analysis using Ansys Apache RedHawk.
• Analyze static/dynamic IR drop, power distribution, current density, and EM violations and drive corrective actions.
• Perform physical verification/signoff using Siemens Calibre, including:
  • DRC
  • LVS
  • ERC
  • Density and related signoff checks
• Coordinate with PD, STA, synthesis, RTL, library, and foundry teams to resolve signoff issues.
• Review and validate signoff methodologies, constraints, corners, libraries, extraction data, and ECO implementation.
• Support timing and physical ECOs and ensure changes do not introduce new signoff violations.
• Participate in full-chip and block-level signoff, including hierarchical timing and physical verification.
• Support tapeout readiness reviews and final signoff documentation.