Senior Physical Design Engineer – SoC & Low-Power

Nutanix; Santa Clara (CA); On-site; USD 135,000 - 202,000; Full time

Job summary

Qualcomm Atheros, Inc. a.k.a. QCA, is a leading wireless technologies provider. This role is part of the Integrated Wireless Technology team, focusing on the complete Physical Design Flow and high-speed, low-power designs. You will contribute to tile-level development, low-power methods, and P&R optimization.

The candidate will engage in floorplanning, place & route, timing closure, ECOs, DFT mode constraints, IR drop analysis, and scripting with Python, PERL/TCL, and Linux shell.

Qualifications

• 2+ years of ASIC physical design experience with tapeout.
• Experience with floorplanning, P&R, and timing closure.
• Knowledge of IR drop, PDN, and power planning.
• Proficiency in scripting languages: Python, PERL/TCL, Linux shell.

Responsibilities

• Innovate, develop, and implement physical design solutions for complex SoCs.
• Manage floorplanning, placement, routing, and timing closure.
• Address DFT constraints, PV violations, and ECOs; support formal verification.

Skills

Physical design

Tapeout experience

Floorplanning

Place & Route (PNR)

Timing closure

ECO implementation

Formal verification

IR drop

Physical verification

Python

PERL/TCL

Linux shell

Education

Bachelor's degree in Science or Engineering

Master's degree in Science or Engineering

PhD in Science or Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Job description

Qualcomm Atheros, Inc. a.k.a. QCA, is a leading wireless technologies provider. This role is part of the Integrated Wireless Technology team, focusing on the complete Physical Design Flow and high-speed, low-power designs. You will contribute to tile-level development, low-power methods, and P&R optimization.

The candidate will engage in floorplanning, place & route, timing closure, ECOs, DFT mode constraints, IR drop analysis, and scripting with Python, PERL/TCL, and Linux shell.