Sr PD Engineer

Qualcomm; Santa Clara (CA); On-site; USD 135,000 - 202,000; Full time

Job summary

Qualcomm Atheros, Inc. is seeking a physical design engineer to join our SOC and core design team in Santa Clara. You will innovate and deliver complex physical design solutions, focusing on tile-level, floorplanning, place & route, and timing closure.

You will work with Cadence Innovus, Synopsys Fusion Compiler, and PTSI, handling IR drop, power planning, DFT constraints, and formal verification to meet area, performance and power goals.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field with 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Responsibilities

• Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
• Tiles level development and enablement of low power implementation methods with P&R optimization.
• Address timing, DFT constraints, floorplanning, power planning and IR drop analysis; fix physical violations and ECOs.
• Design, verify, and deliver complex Physical Design solutions from netlist to final product.

Skills

Physical design

Tapeout experience

Floorplanning

Place & Route

Timing closure

DFT

IR drop/Power

Formal verification

Physical verification

Scripting (Python)

Linux shell

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PTSI

Job description

Company:

Qualcomm Atheros, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs.

Responsibilities:

• Qualcomm’s Connectivity SoC organization is seeking candidates for physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
• Tasks also involve the tiles level development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals.
• Additional responsibilities in this role involves the experience of
  • functional and test (DFT) mode constraints for place and route,
  • floorplanning, power planning
  • IR drop analysis
  • routing, timing optimization and closure
  • implementing timing fixes and functional ECOs
  • debugging and fixing physical violations and formal verification.
• The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell.
• This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

Required Skill/experience:

• 2+ years industry experience in the following areas
  • Tiles level or sub-system level or SoC top level physical design successful tapeout experience
  • Floorplanning of macro cells
  • Place & Route (PNR) tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
  • Timing closure (STA) experience in Synopsys PTSI
  • Function ECO implementation
  • Formal verification (FV) experience
  • Power domain analysis (IR Drop/PDN) experience
  • Physical verification (PV) experience

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$134,500.00 - $201,700.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.