Low Power SoC Design & Methodology Engineer

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Competitive annual discretionary bonus

Opportunity for annual RSU grants

Highly competitive benefits package

Job summary

Qualcomm is seeking a skilled ASIC Designer to focus on adaptive power management solutions in San Diego, California. You will conduct RTL design, simulation, and verification, ensuring high-performance power management in its wireless SoC products.

The ideal candidate will have 3+ years of low power digital ASIC design experience, be familiar with scripting languages, and possess strong analytical skills in electrical engineering. Competitive pay and benefits are part of the package.

Qualifications

• 3 years of experience in low power digital ASIC design.
• Familiar with ASIC front-end design process.
• Proficiency in Verilog/System Verilog coding and scripting languages.

Responsibilities

• Design adaptive power management controller.
• Perform RTL design and verification for IP blocks.
• Work closely with teams to complete the IP design implementation.

Skills

Low power ASIC design

RTL coding

Scripting (Python, Perl, TCL)

Circuit analysis

SoC architecture understanding

Education

Masters or PhD in Electrical or Computer Engineering

Tools

Verilog/System Verilog

UPF

Power aware DV

Job description

Qualcomm is seeking a skilled ASIC Designer to focus on adaptive power management solutions in San Diego, California. You will conduct RTL design, simulation, and verification, ensuring high-performance power management in its wireless SoC products.

The ideal candidate will have 3+ years of low power digital ASIC design experience, be familiar with scripting languages, and possess strong analytical skills in electrical engineering. Competitive pay and benefits are part of the package.