Senior Physical Design Engineer – SoC/ASIC

Qualcomm; Santa Clara (CA); On-site; USD 135,000 - 202,000; Full time

Job summary

Qualcomm Atheros, Inc. is seeking a physical design engineer to join our SOC and core design team in Santa Clara. You will innovate and deliver complex physical design solutions, focusing on tile-level, floorplanning, place & route, and timing closure.

You will work with Cadence Innovus, Synopsys Fusion Compiler, and PTSI, handling IR drop, power planning, DFT constraints, and formal verification to meet area, performance and power goals.

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field with 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Responsibilities

• Innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
• Tiles level development and enablement of low power implementation methods with P&R optimization.
• Address timing, DFT constraints, floorplanning, power planning and IR drop analysis; fix physical violations and ECOs.
• Design, verify, and deliver complex Physical Design solutions from netlist to final product.

Skills

Physical design

Tapeout experience

Floorplanning

Place & Route

Timing closure

DFT

IR drop/Power

Formal verification

Physical verification

Scripting (Python)

Linux shell

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PTSI

Job description

Qualcomm Atheros, Inc. is seeking a physical design engineer to join our SOC and core design team in Santa Clara. You will innovate and deliver complex physical design solutions, focusing on tile-level, floorplanning, place & route, and timing closure.

You will work with Cadence Innovus, Synopsys Fusion Compiler, and PTSI, handling IR drop, power planning, DFT constraints, and formal verification to meet area, performance and power goals.