Design Engineer (Low Power)

Qualcomm; Santa Clara (CA); On-site; USD 176,300 - 264,500; Full time

Benefits offered by this job

Competitive salary

Annual discretionary bonus program

Annual RSU grants

Job summary

A leading technology company based in Santa Clara, California is looking for an experienced ASIC Design Engineer to join their Integrated Wireless Technology team. As a key contributor, you will develop micro-architecture specifications and design low-power solutions within the full ASIC development cycle. Candidates should have significant experience in ASIC design, low power strategies, and silicon debug. This role offers a competitive salary and benefits package, reflecting Qualcomm's commitment to its employees.

Qualifications

• 7+ years of working experience in ASIC Design.
• 2+ years in low power micro-architecture, Design, Power Intent/Implementation.
• Experience in silicon bring up and debug is a must.

Responsibilities

• Develop technical specifications from architectural requirements.
• Deliver detailed low power micro-architecture and design.
• Participate in debug phase and develop verification plans.

Skills

ASIC Design

Low Power Micro-architecture

Power Intent/Implementation

Power Reduction Techniques

SoC Design

Silicon Bring Up

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

AMBA bus protocols

PCIE/USB peripherals

Job description

Company: Qualcomm Atheros, Inc.

Job Area: Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast paced Integrated Wireless Technology team you will be working on WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction techniques.

The candidate will be responsible to develop technical specifications from Architectural and systems requirements and deliver detailed low power micro-architecture and design. Also work closely with verification team to develop verification plans and actively participate in debug phase. The candidate will work hands-on and own their design through the full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is also responsible for the silicon power measurements, Si debug and power correlation. The candidate will also be responsible for the full chip debug design using ARM IPs.

Experience in SoC low power micro-architecture, low power design and methodology, Power Intent/Implementation, power estimates, power analysis tools and power reduction techniques is a must. Experience in ARM IP based full chip debug is preferred.

• 7+ years of working experience in ASIC Design
• 2+ years of Experience in low power micro-architecture, Design, Power Intent/Implementation, power optimization and power estimation
• Experience in silicon bring up and debug is a must
• Required experience on SoC micro architecture, multi-domain clocking, AMBA bus protocols such as AHB and APB. AXI is preferred
• Experience in ARM IP based full chip debug is preferred
• Experience in PCIE/USB peripherals is preferred
• Experience in CPU sub system-based design is preferred
• Experience in low power design from project start to volume chip production for at least one product cycle is preferred

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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Pay range and Other Compensation & Benefits

$176,300.00 - $264,500.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.