Senior ASIC Design Engineer - Low-Power SOC & WiFi

Anysilicon; Santa Clara (CA); Hybrid; USD 120,000 - 150,000; Full time

Job summary

Qualcomm Atheros, Inc. in Santa Clara, CA seeks an experienced ASIC Design Engineer to develop low-power micro-architecture for WiFi SOCs, spanning from specs to post-silicon bring-up. You will drive the design through RTL, verification, timing, and power analysis.

You will collaborate with the verification team to craft verification plans, perform silicon power measurements, and lead silicon bring-up and debug activities across multi-domain clocking and AMBA protocols.

Qualifications

• 4+ years of ASIC design experience.
• Experience with low-power micro-architecture and design methodology.
• Proficiency with power intent/implementation and power analysis tools.

Responsibilities

• Develop technical specifications from architectural and systems requirements.
• Deliver detailed low power micro-architecture and design.
• Collaborate with the verification team to create verification plans and participate in the debug phase.
• Own design through the full ASIC development process including specification, RTL implementation, verification, synthesis, timing closure, emulation, and post-silicon bring-up.
• Conduct silicon power measurements, silicon debug, and power correlation.

Skills

Low-power design

Power analysis tools

Silicon bring-up

AMBA protocols

ARM IP & PCIe/USB

Education

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Job description

Qualcomm Atheros, Inc. in Santa Clara, CA seeks an experienced ASIC Design Engineer to develop low-power micro-architecture for WiFi SOCs, spanning from specs to post-silicon bring-up. You will drive the design through RTL, verification, timing, and power analysis.

You will collaborate with the verification team to craft verification plans, perform silicon power measurements, and lead silicon bring-up and debug activities across multi-domain clocking and AMBA protocols.