Physical Design Engineer – ASIC/SoC

Qualcomm; San Diego (CA); On-site; USD 99,000 - 148,000; Full time

Benefits offered by this job

Annual bonus program

RSU grants

Comprehensive benefits package

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC Engineer in San Diego to define, model, and design digital and/or analog IP/SoC blocks. You will optimize and verify IP to meet high-performance, low-power requirements and document the development process.

Collaborating with cross-functional teams, you will drive architecture, circuit specs, and system simulations from concept through implementation, while ensuring robust verification and integration across product lines.

Qualifications

• Bachelor's degree in Science/Engineering with 2+ years ASIC experience.
• Master's degree with 1+ year ASIC experience.
• PhD in Science/Engineering.

Responsibilities

• Define, model, design (digital/analog) and optimize IP/SoC development for high-performance, low-power products.
• Create architectures, circuit specs, logic designs, and simulations from system requirements.
• Collaborate with software and hardware teams to meet system requirements and customer needs.
• Evaluate process flow from design to verify and validate, ensuring timing and power goals.
• Write technical documentation for EDA/IP/ASIC projects.

Skills

ASIC design

Verification

Validation

IP integration

Documentation

Education

Bachelor's degree in Science or Engineering

Master's degree in Science or Engineering

PhD in Science or Engineering

Tools

RTL to GDS Flow

Virtuoso

EDA tools

Job description

Qualcomm Technologies, Inc. is seeking an ASIC Engineer in San Diego to define, model, and design digital and/or analog IP/SoC blocks. You will optimize and verify IP to meet high-performance, low-power requirements and document the development process.

Collaborating with cross-functional teams, you will drive architecture, circuit specs, and system simulations from concept through implementation, while ensuring robust verification and integration across product lines.