Senior Physical Design Engineer - RTL-to-GDS, High-Perf IP

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking a collaborative Physical Design Engineer to help drive RTL-to-GDS flow for high-performance IP blocks.

You will work across synthesis, floorplanning, timing-driven place and route, clock tree synthesis, and signoff with distributed teams to deliver quality silicon on schedule. The ideal candidate combines strong technical curiosity with effective communication, balancing timing, power, area, and reliability while improving design

Qualifications

• Bachelor's or master's in electrical engineering, CS, or related field.
• Academic or professional exposure to high-speed SerDes PHY or high-performance IP is valued.
• Experience with RTL-to-GDS flow and standard physical design steps is preferred.

Responsibilities

• Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.
• Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities.
• Analyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.
• Support floorplanning, design methodology development, and integration of complex IP.
• Perform and support logic equivalence, timing, physical, and electrical quality checks.
• Troubleshoot implementation and timing challenges and collaborate with design teams to drive issues to closure.
• Identify opportunities to improve automation, design methodology, quality, and overall design cycle time.
• Support final signoff and delivery of large, high-performance IP blocks.
• Build familiarity with the team's design environment and methodologies early in the role, progressing toward independent ownership of physical design blocks and optimization activities.

Skills

Collaboration

Communication

Problem solving

Cross-functional teamwork

Education

Bachelor's or Master's in Electrical Engineering / Computer Science

Tools

RTL-to-GDS flow

Synthesis

Floorplanning

Timing-driven place & route

Clock tree synthesis

Physical verification

Final sign-off

Verilog

EDA tools

IP integration

Timing analysis

Job description

Advanced Micro Devices, Inc. in Santa Clara, CA is seeking a collaborative Physical Design Engineer to help drive RTL-to-GDS flow for high-performance IP blocks.

You will work across synthesis, floorplanning, timing-driven place and route, clock tree synthesis, and signoff with distributed teams to deliver quality silicon on schedule. The ideal candidate combines strong technical curiosity with effective communication, balancing timing, power, area, and reliability while improving design