Senior Physical Design Engineer – High-Performance PHY

Apple, Inc.; Cupertino (CA); Presencial; USD 150 000 - 278 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical and dental coverage

Employee stock programs

Retirement benefits

Relocation assistance

Resumo da oferta

Apple, Inc. is seeking a forward-thinking Physical Design Engineer in Cupertino to contribute to high-performance PHY design from RTL to GDSII. You will collaborate with architecture, CAD, timing and logic teams to deliver optimized PHY blocks and full-chip flows.

The role emphasizes floor-planning, place & route, power-grid and clock specification development, plus ECO creation and timing closure across SOC designs. A strong background in Verilog, STA and scripting is required.

Qualificações

• Bachelor's degree in Electrical Engineering with 3+ years of relevant industry experience or equivalent.
• Deep knowledge of physical design flows, from RTL to GDSII, and experience with timing closure.

Responsabilidades

• Generate block/chip level timing constraints.
• Design full chip floor-plans including pin placement and power grid.
• Perform block-level place & route to meet timing, area and power constraints.
• Generate and implement ECOs to fix timing, noise and EM/IR issues.
• Run physical design verification flow and guide LVS/DRC debugging.

Conhecimentos

PHY design

SOC designs

Physical Design

Power/grid specs

Clock specs

Verilog HDL

Perl/Tcl scripting

STA/Extraction

LVS/DRC debugging

SoC architecture

Formação académica

B.S. in Electrical Engineering

Descrição da oferta de emprego

Apple, Inc. is seeking a forward-thinking Physical Design Engineer in Cupertino to contribute to high-performance PHY design from RTL to GDSII. You will collaborate with architecture, CAD, timing and logic teams to deliver optimized PHY blocks and full-chip flows.

The role emphasizes floor-planning, place & route, power-grid and clock specification development, plus ECO creation and timing closure across SOC designs. A strong background in Verilog, STA and scripting is required.