Senior Physical Design Engineer — RTL-to-GDS & Performance

Intel; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Paid vacation

Job summary

Intel is seeking a Physical Design Engineer to drive cutting-edge semiconductor designs from RTL to GDS. You will deliver high-performance physical designs, optimize power, performance, and area, and work with CAD and PD teams to adopt best-in-class tools.

The role spans floor planning, timing closure, and membrane-level optimizations, with emphasis on memory macro optimization and standard cell efficiency. This position supports our hybrid work model in the US.

Qualifications

• Bachelor's or Master's degree with PD experience.
• Experience in floor planning and timing constraints definition.
• Scripting for design flow automation (Python, Perl, TCL).
• FEV/RV debugging and ECOs handling experience.
• Chiplet integration and advanced packaging familiarity.
• AI tools to optimize workflows and debugging.

Responsibilities

• Drive RTL-to-GDS design convergence with advanced synthesis and place-and-route.
• Deliver block-level physical design and backend flow closure.
• Collaborate with CAD and PD teams to adopt industry tools and optimizations.
• Perform floor planning, bus/pin placement, power/clock distribution, and timing closure.
• Debug timing, EM/IR, LVS, DRC and drive sign-off for high-quality silicon.
• Collaborate with IP teams to optimize memory macros and standard cells.
• Develop and refine PD methodologies to boost productivity.

Skills

Floor planning and timing constraints

Synthesis and place-and-route

Python/Perl/TCL scripting

FEV/RV debugging and ECOs

Chiplet integration and advanced

AI tools for design workflows

Cross-functional collaboration

Power-efficient and high-frequency PD

Java or C++ OO programming

Asynchronous architectures knowledge

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree in Electrical Engineering or related field

Tools

Cadence Virtuoso

Synopsys Fusion Compiler

Job description

Intel is seeking a Physical Design Engineer to drive cutting-edge semiconductor designs from RTL to GDS. You will deliver high-performance physical designs, optimize power, performance, and area, and work with CAD and PD teams to adopt best-in-class tools.

The role spans floor planning, timing closure, and membrane-level optimizations, with emphasis on memory macro optimization and standard cell efficiency. This position supports our hybrid work model in the US.