Sr Physical Design Engineer

AMD; Santa Clara (CA); On-site; USD 180,000 - 230,000; Full time

Job summary

AMD in Santa Clara seeks a collaborative Physical Design Engineer to drive RTL-to-GDS implementation for high-performance SerDes IP. You will contribute across synthesis, floorplanning, timing-driven place and route, clock tree synthesis, and sign-off, coordinating with distributed teams to deliver complex IP with high quality.

You will apply automated flows, analyze timing, power, and area, support design methodology, and push scalable engineering flows.

Qualifications

• Collaborative engineer with clear communication and technical curiosity.
• Analytical approach to balancing timing, power, area, and schedule.
• Able to prioritize work across multiple projects and teams.

Responsibilities

• Drive physical implementation of RTL blocks through synthesis, floorplanning, and signoff.
• Develop automated flows for clock tree synthesis, power gating, and related tasks.
• Analyze and optimize timing, power, and area targets.
• Support floorplanning and IP integration in complex designs.
• Perform and support timing, physical, and electrical checks.
• Collaborate with design teams to resolve timing challenges.
• Identify opportunities to improve automation and design methodologies.
• Support final signoff and delivery of large IP blocks.
• Learn and adapt to the team’s design environment early in the role.

Skills

Collaborative engineer

Clear communication

Analytical problem solving

Project prioritization

Tools

Verilog

EDA tools

Synthesis/Place & Route

Physical verification

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

Join a team developing high-performance, multi-gigabit SerDes PHY and advanced IP designs. In this Physical Design Engineering role, you will contribute across the full RTL-to-GDS implementation lifecycle, working on challenging designs where timing, power, area, and physical quality are critical. You will collaborate with geographically distributed engineering teams and gain exposure to synthesis, floorplanning, timing-driven place and route, clock tree synthesis, physical verification, and final sign off. This is an opportunity to influence both individual designs and the methodologies and automated flows used to deliver complex IP efficiently and with high quality.

The Person

The successful candidate is a collaborative and technically curious engineer who enjoys solving complex physical design challenges. You communicate technical concepts clearly, work effectively with colleagues across different disciplines and locations, and can prioritize work across multiple projects. You bring a thoughtful, analytical approach to problem solving and are comfortable balancing timing, power, area, quality, and schedule considerations. You are also interested in improving design methodologies and identifying opportunities to make engineering flows more efficient and scalable.

Key Responsibilities

• Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.
• Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities.
• Analyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.
• Support floorplanning, design methodology development, and integration of complex IP.
• Perform and support logic equivalence, timing, physical, and electrical quality checks.
• Troubleshoot implementation and timing challenges and collaboration with design teams to drive issues to closure.
• Identify opportunities to improve automation, design methodology, quality, and overall design cycle time.
• Support final signoff and delivery of large, high-performance IP blocks.
• Build familiarity with the team's design environment and methodologies early in the role, progressing toward independent ownership of physical design blocks and optimization activities.

Preferred Experience

• Experience taking digital designs through the RTL-to-GDS physical design flow.
• Experience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs is preferred.
• Experience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic.
• Verilog experience is preferred.
• Experience with clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and design optimization.
• Knowledge of timing, power, and area optimization techniques.
• Understanding of digital circuit techniques, logic optimization, and implementation approaches for high-speed, low-power applications.
• Experience with floorplanning, IP integration, logic equivalence checking, physical verification, timing analysis, electrical quality checks, and final signoff.
• Experience with industry EDA tools for logic synthesis, place and route, static timing analysis, and physical/electrical design checks.
• Familiarity with schematic, layout, circuit simulation, or logic simulation tools is desired.