Senior Physical Design Engineer — Remote (GF 12LP)

Encore Semi Llc; Chandler (AZ); Remote; USD 135,000 - 165,000; Full time

Benefits offered by this job

15 days PTO

10 paid Holidays

Medical benefits (Company covers 80%+)

Dental & Vision (Company covers 50%+)

Life Insurance & LTD

401k - Traditional & Roth

Tuition reimbursement

Job summary

Encore Semi is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for high-performance SoCs on GF 12LP. The role emphasizes owning advanced FinFET design challenges, pushing PPA, and driving timing closure in a 12LP node environment.

You will work on end-to-end physical design from synthesis to GDSII signoff using Fusion Design Platform, including floorplanning, CTS, and routing, with emphasis on robust STA and signoff methodologies.

Qualifications

• 5+ years of ASIC physical design experience with tape-outs on advanced FinFET nodes
• GF 12LP experience or familiarity is a plus
• Strong RTL-to-GDSII workflow knowledge and design-for-signoff practices

Responsibilities

• Drive block- and top-level physical design from synthesis through GDSII signoff using Fusion Design Platform
• Execute floorplanning, power grid design, placement, CTS, and detailed routing for GF 12LP architectures
• Lead STA, parasitic extraction, and multi-corner/multi-mode timing closure
• Resolve FinFET physical challenges including DRC/LVS and EM/IR-drop analysis
• Develop Tcl and Python scripts to streamline flows and track PPA metrics

Skills

ASIC physical design

Synopsys Fusion Compiler

PrimeTime

Scripting: Tcl/Python/Perl

STA/Timing analysis

Education

BS or MS in Electrical Engineering

Tools

Synopsys Fusion Compiler

PrimeTime

Job description

Encore Semi is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for high-performance SoCs on GF 12LP. The role emphasizes owning advanced FinFET design challenges, pushing PPA, and driving timing closure in a 12LP node environment.

You will work on end-to-end physical design from synthesis to GDSII signoff using Fusion Design Platform, including floorplanning, CTS, and routing, with emphasis on robust STA and signoff methodologies.