Senior Physical Design Engineer - 100% Remote (GF 12LP)

Encore Semi Llc; Austin (TX); Teletrabalho; USD 135 000 - 165 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

PTO 15 days

Holidays 10

Medical benefits 80%

Dental & Vision 50%

401k Traditional & Roth

Life/AD&D & LTD

Tuition reimbursement

EAP

Resumo da oferta

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs. You will own advanced FinFET design challenges, push PPA boundaries, and drive robust timing closure on GF 12LP nodes.

You will perform floorplanning, CTS, detailed routing, STA, parasitic extraction, and signoff using Fusion Design Platform and PrimeTime, while developing Tcl/Python scripts to streamline flows and track PPA metrics.

Qualificações

• 5+ years of ASIC physical design experience with proven tape-outs on advanced FinFET nodes (≤14nm/12nm).
• Deep hands-on proficiency with Synopsys Fusion Compiler (or ICC II) and PrimeTime.
• Strong grounding in synthesis, CTS, complex SDC constraints, and signoff methodologies.
• Scripting skills in Tcl, Python, or Perl.
• BS or MS in Electrical/Computer Engineering or related field.

Responsabilidades

• End-to-End Implementation: Drive block- and top-level physical design from synthesis through GDSII signoff using the Fusion Design Platform.
• Core P&R & Optimization: Floorplanning, power grid design, placement, CTS, and routing for GF 12LP architectures.
• Timing & Signoff: Lead STA, parasitic extraction, and multi-corner/multi-mode closure with PrimeTime and StarRC.
• Physical Verification & Reliability: Address FinFET challenges, DRC/LVS, EM/IR-drop analysis.
• Automation: Develop Tcl and Python scripts to streamline flows and track PPA metrics.

Conhecimentos

ASIC physical design

Tape-out experience

Scripting

Formação académica

BS or MS in Electrical/Computer Engineering

Ferramentas

Synopsys Fusion Compiler

PrimeTime

ICC II

StarRC

Descrição da oferta de emprego

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs. You will own advanced FinFET design challenges, push PPA boundaries, and drive robust timing closure on GF 12LP nodes.

You will perform floorplanning, CTS, detailed routing, STA, parasitic extraction, and signoff using Fusion Design Platform and PrimeTime, while developing Tcl/Python scripts to streamline flows and track PPA metrics.