Senior Physical Design Engineer — Remote (GF 12LP)

Encore Semi Llc; Burlington (VT); Remote; USD 135,000 - 165,000; Full time

Benefits offered by this job

15 days PTO

10 paid Holidays

Medical benefits: 80% premiums

Dental & Vision 50% premiums

Life Insurance, FSA/HAS

401k - Traditional & Roth

EAP

Long-Term Disability

Tuition reimbursement

Job summary

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for GF 12LP cores, owning advanced FinFET design challenges and driving robust timing closure.

This is a 100% remote, US-based role with a salary between $135,000 and $165,000 plus comprehensive benefits. 5+ years of ASIC physical design, Fusion Compiler and PrimeTime expertise, and Tcl/Python scripting are required.

Qualifications

• 5+ years ASIC physical design experience with tape-outs on FinFET nodes.
• Proficient with Synopsys Fusion Compiler or ICC II and PrimeTime.
• Strong grounding in synthesis, CTS, SDC constraints, and signoff.
• Scripting skills in Tcl or Python or Perl.
• BS or MS in Electrical or Computer Engineering or related field.

Responsibilities

• End-to-End Implementation: drive block- and top-level physical design from synthesis through GDSII signoff.
• Lead P&R optimization: floorplanning, power grid, placement, CTS, routing.
• Lead STA, parasitic extraction, multi-corner/multi-mode closure.
• Address FinFET reliability: DRC/LVS, EM/IR-drop analysis.
• Develop Tcl and Python scripts to streamline flows and track PPA metrics.

Skills

ASIC physical design

Tape-out experience

Scripting: Tcl/Python

Timing analysis

Power/RT constraints

Education

BS/MS Electrical Engineering

Tools

Synopsys Fusion Compiler

PrimeTime

StarRC

IC Compiler

Job description

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for GF 12LP cores, owning advanced FinFET design challenges and driving robust timing closure.

This is a 100% remote, US-based role with a salary between $135,000 and $165,000 plus comprehensive benefits. 5+ years of ASIC physical design, Fusion Compiler and PrimeTime expertise, and Tcl/Python scripting are required.