Senior Physical Design Engineer – Remote (GF 12LP)

Encore Semi, Inc.; Burlington (VT); Remote; USD 135,000 - 165,000; Full time

Benefits offered by this job

PTO 15 days

10 paid Holidays

Medical benefits

Dental & Vision coverage

Life Insurance

401k

Job summary

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for high-performance SoCs on GF 12LP. You will own FinFET design challenges, push PPA boundaries, and drive robust timing closure. Remote in USA with US citizenship required.

You will drive end-to-end P&R, CTS, and routing, lead STA and signoff, and develop scripts to automate flows. 5+ years of ASIC design experience and strong tool mastery are required.

Qualifications

• 5+ years of ASIC physical design experience with tape-outs on FinFET nodes (≤14nm/12nm).
• BS or MS in Electrical/Computer Engineering.
• Strong SDC constraints and signoff methodologies.
• Proficiency with Tcl, Python, or Perl scripting.

Responsibilities

• Drive block- and top-level physical design from synthesis through GDSII signoff using the Synopsys Fusion Design Platform.
• Execute floorplanning, power grid design, placement, CTS, and detail routing optimized for GF 12LP standard cell architectures.
• Lead Static Timing Analysis (STA), parasitic extraction, and multi-corner/multi-mode closure using PrimeTime and StarRC.
• Resolve advanced FinFET physical challenges, including double patterning, DRC/LVS, and EM/IR-drop analysis.
• Develop Tcl and Python scripts to streamline flows, improve runtimes, and track PPA metrics.

Skills

ASIC Physical Design

Floorplanning

CTS

Power integrity

Timing closure

Scripting Tcl/Python

GF 12LP FinFET

Fusion Compiler/ICC

PrimeTime

Education

BS or MS in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

PrimeTime

ICC II

StarRC

Job description

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for high-performance SoCs on GF 12LP. You will own FinFET design challenges, push PPA boundaries, and drive robust timing closure. Remote in USA with US citizenship required.

You will drive end-to-end P&R, CTS, and routing, lead STA and signoff, and develop scripts to automate flows. 5+ years of ASIC design experience and strong tool mastery are required.