Lead End-to-End Physical Design for GF 12LP (Remote)

Encore Semi, Inc.; United States; Remote; USD 135,000 - 165,000; Full time

Benefits offered by this job

15 days PTO

10 holidays

Medical benefits (80% premiums)

Dental & Vision (50% premiums)

Voluntary benefits

Life Insurance & LTD

Job summary

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for high‑performance SoCs on GF 12LP. You will own FinFET design challenges, drive PPA improvements, and push timing closure for robust performance.

The role requires hands‑on experience with Synopsys Fusion Compiler and PrimeTime, plus scripting in Tcl or Python. Remote work in the USA is supported with a comprehensive benefits package.

Qualifications

• Minimum 5+ years of ASIC physical design experience.
• Proficient in RTL-to-GDSII flow and signoff.
• Strong scripting abilities in Tcl, Python, or Perl.

Responsibilities

• Lead end-to-end physical design from synthesis to GDSII signoff.
• Perform floorplanning, power grid design, placement, CTS, and routing optimizations.

Skills

ASIC physical design

Scripting (Tcl/Python/Perl)

Timing closure

CTS knowledge

Education

BS/MS in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

PrimeTime

ICC II

Job description

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for high‑performance SoCs on GF 12LP. You will own FinFET design challenges, drive PPA improvements, and push timing closure for robust performance.

The role requires hands‑on experience with Synopsys Fusion Compiler and PrimeTime, plus scripting in Tcl or Python. Remote work in the USA is supported with a comprehensive benefits package.