Senior Physical Design Engineer - Remote (GF 12LP)

Encore Semi Llc; Raleigh (NC); Remoto; USD 135.000 - 165.000; Tempo pieno

Vantaggi offerti da questo lavoro

PTO 15 days/year

Holidays 10 per year

Medical benefits 80% premium coverage

Dental & Vision 50% coverage

Life Insurance & Disability

401k

Descrizione del lavoro

Encore Semi, Inc. seeks a Senior Physical Design Engineer to lead RTL-to-GDSII for GF 12LP-based SoCs in a 100% remote role in the USA. You will own advanced FinFET physical design challenges, drive PPA improvements, and deliver robust timing closure using Fusion Compiler and PrimeTime.

The role requires 5+ years of ASIC PD experience with GF 12nm/14nm tape-outs, scripting in Tcl/Python, and a BS/MS in EE or CE. Competitive salary with full benefits and remote work nationwide.

Competenze

• 5+ years of ASIC physical design experience with tape-outs on FinFET nodes.
• Hands-on proficiency with Synopsys Fusion Compiler (or ICC II) and PrimeTime.
• Strong grounding in synthesis, CTS, SDC constraints, and signoff methodologies.
• Scripting skills in Tcl and Python (or Perl).
• BS or MS in Electrical or Computer Engineering or related field.

Mansioni

• End-to-End implementation: drive block- and top-level physical design from synthesis to GDSII signoff using Fusion.Design Platform.
• Core P&R & optimization: floorplanning, power grid design, placement, CTS, and routing for GF 12LP nodes.
• Timing & signoff: lead STA, extraction, multi-corner/multi-mode closure with PrimeTime/StarRC.
• Physical verification & reliability: address FinFET challenges, DRC/LVS, EM/IR-drop with RedHawk.
• Automation: develop Tcl and Python scripts to streamline flows and track PPA metrics.

Descrizione del lavoro

Encore Semi, Inc. seeks a Senior Physical Design Engineer to lead RTL-to-GDSII for GF 12LP-based SoCs in a 100% remote role in the USA. You will own advanced FinFET physical design challenges, drive PPA improvements, and deliver robust timing closure using Fusion Compiler and PrimeTime.

The role requires 5+ years of ASIC PD experience with GF 12nm/14nm tape-outs, scripting in Tcl/Python, and a BS/MS in EE or CE. Competitive salary with full benefits and remote work nationwide.