Senior Physical Design Engineer — Remote, GF 12LP

Encore Semi Llc; Hillsboro (OR); A distancia; USD 135.000 - 165.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

PTO 15 days

Holidays 10

Medical benefits 80% premiums

Dental & Vision 50% premiums

Voluntary benefits

EAP

401k

Life/AD&D & LTD

Tuition reimbursement

Descripción de la vacante

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for GF 12LP. You’ll drive advanced FinFET challenges, push PPA boundaries, and own robust timing closure across a remote US team.

The role requires 5+ years in ASIC physical design, proficiency with Fusion Compiler and PrimeTime, and scripting in Tcl/Python/Perl. Competitive salary with full benefits, and a 100% remote work setup nationwide.

Formación

• 5+ years of ASIC physical design experience with tape-outs on FinFET nodes (≤14nm/12nm).
• Deep hands-on proficiency with Synopsys Fusion Compiler (or ICC II) and PrimeTime.
• Strong grounding in synthesis, CTS, SDC constraints, and signoff methods.
• Scripting skills in Tcl, Python, or Perl.
• BS or MS in Electrical or Computer Engineering.

Responsabilidades

• End-to-End Implementation: drive block- and top-level physical design from synthesis through GDSII signoff.
• Core P&R & Optimization: floorplanning, power grid design, placement, CTS, routing for GF 12LP.
• Timing & Signoff: lead STA, parasitic extraction, multi‑corner/multi‑mode closure (PrimeTime/StarRC).
• Physical Verification & Reliability: address FinFET challenges, DRC/LVS, EM/IR-drop analysis.
• Automation: develop Tcl and Python scripts to streamline flows and track PPA metrics.

Conocimientos

ASIC physical design

Scripting Tcl/Python/Perl

Timing closure

Floorplanning

CTS

DRC/LVS

Tape-out experience

Educación

BS or MS in Electrical/Computer Engineering

Herramientas

Synopsys Fusion Compiler

PrimeTime

ICC II

Descripción del empleo

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for GF 12LP. You’ll drive advanced FinFET challenges, push PPA boundaries, and own robust timing closure across a remote US team.

The role requires 5+ years in ASIC physical design, proficiency with Fusion Compiler and PrimeTime, and scripting in Tcl/Python/Perl. Competitive salary with full benefits, and a 100% remote work setup nationwide.