Senior Physical Design Engineer Remote GF12LP Expert

Encore Semi, Inc.; Rochester (MN); Remote; USD 135,000 - 165,000; Full time

Benefits offered by this job

PTO 15 days

Holidays 10

Medical benefits

Dental & Vision

Voluntary benefits

EAP

401k

Life/AD&D

Tuition reimbursement

Job summary

Encore Semi, Inc. seeks a Senior Physical Design Engineer to own RTL-to-GDSII for high-performance SoCs, targeting GlobalFoundries 12LP nodes. This role is remote in the USA, with full-time salary, benefits, and bonuses.

You will drive floorplanning, CTS, and routing, oversee STA and signoff, and develop automation to improve PPA and runtimes. Requires 5+ years ASIC PD and strong scripting skills.

Qualifications

• 5+ years ASIC physical design experience with tape-outs on FinFET nodes (≤14nm/12nm).
• GF 12LP knowledge or experience preferred.
• Strong SDC constraints, CTS, and signoff methodologies.

Responsibilities

• End-to-End implementation from synthesis to GDSII signoff using Fusion Design Platform.
• Floorplanning, power grid design, placement, CTS, routing for GF 12LP cell architectures.
• Lead STA, parasitic extraction, and multi-corner/multi-mode closure with PrimeTime.
• Resolve FinFET physical challenges including DRC/LVS and EM/IR-drop analysis.
• Develop Tcl and Python scripts to streamline flows and track PPA metrics.

Skills

ASIC physical design

RTL-to-GDSII ownership

Scripting (Tcl/Python/Perl)

Timing closure

Interfacing with flows

Education

BS or MS in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

ICC II

PrimeTime

StarRC

RedHawk

Job description

Encore Semi, Inc. seeks a Senior Physical Design Engineer to own RTL-to-GDSII for high-performance SoCs, targeting GlobalFoundries 12LP nodes. This role is remote in the USA, with full-time salary, benefits, and bonuses.

You will drive floorplanning, CTS, and routing, oversee STA and signoff, and develop automation to improve PPA and runtimes. Requires 5+ years ASIC PD and strong scripting skills.