Physical Design Engineer – Staff/Principal

Chiparama; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Chiparama Inc. in San Jose, CA, is seeking a Senior Physical Design Engineer to own RTL-to-GDSII implementation for advanced nodes. You will lead floorplanning, placement, CTS, routing, clocking and signoff while shaping PD methodologies for right-first-time silicon.

You will drive timing closure, constraints, STA, and power-aware design across blocks and full-chip, mentor junior engineers and collaborate with CAD, IP, library, and packaging teams to resolve issues on schedule.

Qualifications

• 12+ years in deep-sub-micron IC physical design with 7nm or below tape-outs.
• Hands-on floorplanning, placement, CTS, routing, timing closure and signoff.
• Strong STA understanding with MCMM closure and cross-talk awareness.
• Expert in industry tool suites (Synopsys or Cadence) for PD.
• Experience with EM/IR and physical verification workflows.
• Proven ability to lead and mentor across global teams.

Responsibilities

• Own physical implementation of blocks, partitions and full-chip.
• Drive timing closure at block and chip level; develop constraints and signoff.
• Meet PPA targets and drive PD tools/methodologies to achieve goals.
• Run physical-aware synthesis, UPF, ES, and signoff activities.
• Develop and automate PD flows using Tcl, Python, Perl and Shell.
• Collaborate with design, DFT, IP, library, packaging and CAD teams.
• Provide technical leadership and mentoring to junior engineers.

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

Physical verification

LVS/DRC

UPF/power gating

Scripting (Tcl/Python)

Leadership

Tape-out experience

Education

BE/BS in EE/CE

MS/ME or PhD in EE/CE

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus/Tempus

Calibre/ICV

RedHawk/Voltus

Job description

Our client is a global semiconductor leader building high-performance ASICs and SoCs for AI, HPC, data center networking, SerDes connectivity and PCIe switch products. They are looking for a senior Physical Design Engineer to own RTL-to-GDSII implementation at advanced nodes (7nm and below, including 5nm/3nm).

About the Role

You will drive PPA, timing closure and signoff at block and top level, and shape the physical design methodology used across programs to deliver right-first-time silicon.

• Own physical implementation of blocks, partitions and full-chip: floorplanning (including multi-power-domain and PG planning), partitioning, placement, clock tree synthesis, routing and optimization
• Drive timing closure at block and chip level: constraints development and validation, STA, signoff, and timing/functional ECOs
• Meet power, performance and area targets; drive tools and methodologies to achieve PPA goals
• Run physical-aware synthesis, formal equivalence checks and low-power (UPF) implementation and signoff
• Perform physical verification (LVS/DRC/ERC/antenna) and EM/IR analysis (static and dynamic IR, signal and power EM)
• Resolve congestion, integration and chip-assembly issues; deliver top-level partitions
• Build custom clock trees with insertion-delay reduction and skew balancing where needed
• Develop and automate PD flows and methodologies using Tcl, Python, Perl and Shell
• Work with design, DFT, IP, library, packaging and CAD teams (internal and external) to close issues on schedule
• Apply a milestone-driven design methodology for right-first-time silicon and support tape-out
• Mentor junior engineers and provide technical leadership on complex implementations
• Opportunity areas: 2.5D/3D die-to-die interconnect and HBM physical implementation

Required Qualifications

• BE/BS plus 12+ years, or ME/MS (or PhD) in EE/CE plus 10+ years, in deep-sub-micron IC physical design (or equivalent experience)
• Multiple full-chip tape-outs at 7nm or below (5nm/3nm preferred)
• Deep, hands-on expertise in floorplanning, placement, CTS, routing, timing closure and physical verification
• Strong STA background including constraints, SI/crosstalk and multi-corner multi-mode (MCMM) closure
• Expert with industry P&R and signoff tools: Synopsys (Fusion Compiler / ICC2, PrimeTime, StarRC, Formality) and/or Cadence (Innovus, Tempus, Voltus, Conformal)
• Experience with EM/IR tools (e.g., RedHawk, Voltus) and physical verification tools (Calibre, ICV, Pegasus)
• Strong scripting and automation skills (Tcl, Python, Perl, Shell)
• Ability to independently own block-level and top-level implementation
• Excellent problem-solving, communication and cross-team collaboration skills in a global environment
• Top-level / chip-level floorplanning and STA ownership experience
• Experience with high-speed designs: SerDes, PCIe, DDR/HBM, Ethernet switch, AI accelerators
• Low-power design methodology (UPF, multi-voltage, power gating)
• Methodology and flow development ownership; prior technical-lead role