Senior Physical Design Engineer Memory-Centric SoC

Conductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Competitive benefits

Fertility/adoption support

Onsite gym and café

Job summary

Samsung Semiconductor in San Jose, CA, seeks a skilled digital physical design engineer to own memory-centric IP and full-chip floorplanning, CTS, and timing closure.

You will collaborate with RTL/verification teams, develop TCL/Python flows, and contribute to AI/ML workloads while advancing PPA, power integrity, and tapeout on advanced FinFET nodes. This role offers a competitive US-wide pay range and comprehensive benefits in a collaborative, global environment.

Qualifications

• Bachelor’s degree plus 5+ years in digital physical design.
• Experience with ASIC/SoC physical design flows and toolchains.
• Proficiency with major EDA tools and scripting for flow automation.

Responsibilities

• Own physical implementation of memory-centric IP and SoC partitions from RTL to GDSII.
• Converge PPA and perform timing closure across process corners.
• Develop floorplans, power networks, and macro placement strategies.
• Perform STA, constraint development, and signoff; resolve timing and SI issues.
• Automate physical design flows with Tcl/Python; collaborate with RTL/verification.
• Communicate with stakeholders to deliver designs on time and within budget.

Skills

Digital physical design

VLSI implementation

Scripting Tcl/Python

AI/ML workloads

Communication skills

LED with EDA tools

Team collaboration

Education

Bachelor’s degree in EE/CS

Master’s degree in EE/CS

PhD

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus

PrimeTime

StarRC

Job description

Samsung Semiconductor in San Jose, CA, seeks a skilled digital physical design engineer to own memory-centric IP and full-chip floorplanning, CTS, and timing closure.

You will collaborate with RTL/verification teams, develop TCL/Python flows, and contribute to AI/ML workloads while advancing PPA, power integrity, and tapeout on advanced FinFET nodes. This role offers a competitive US-wide pay range and comprehensive benefits in a collaborative, global environment.