Senior SOC Design Engineer – Memory & SoC

Samsung-Semiconductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

4+ weeks paid time off

Medical/Dental/Vision/401k

Fertility/adoption support

Emotional wellness programs

Onsite café and gym

Job summary

Samsung Semiconductor is hiring a Principal Engineer, SOC Design to lead architectural and RTL development for next-gen memory-focused SoCs. You will drive micro-architecture, integrate third-party IPs like ARM cores and DDR controllers, and collaborate with architects and verification engineers to ensure robust designs.

You will work with physical design on timing, synthesis, DFT, and STA, shaping product roadmaps for memory and storage solutions in a collaborative, innovation-driven

Qualifications

• BS/MS/PhD in Electrical or Computer Science with significant industry experience.
• Strong communication and collaboration in a multi-disciplinary team.
• Hands-on ASIC design flow from design to tape out.

Responsibilities

• Participate in architectural definitions and micro-architecture of subsystems.
• Lead top-level integration and RTL implementation with quality checks.
• Review third-party IPs including ARM cores and DDR controllers.
• Integrate IPs and subsystems at top level with verification teams.
• Collaborate with physical designers on timing, synthesis, and STA.

Skills

ASIC design flow

AMBA bus fabric

UCIe IPs

DDR controller

RTL design

Timing analysis

Synthesis

DFT/PI/PD interfacing

Education

Bachelors in Electrical/Computer Science or related

Masters in Electrical/Computer Science or related

PhD in Electrical/Computer Science or related

Tools

AMBA bus fabric

UCIe

DDR controllers

Job description

Samsung Semiconductor is hiring a Principal Engineer, SOC Design to lead architectural and RTL development for next-gen memory-focused SoCs. You will drive micro-architecture, integrate third-party IPs like ARM cores and DDR controllers, and collaborate with architects and verification engineers to ensure robust designs.

You will work with physical design on timing, synthesis, DFT, and STA, shaping product roadmaps for memory and storage solutions in a collaborative, innovation-driven