Senior SOC Design Engineer, Memory & SoC Architect

Samsung Semiconductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

4+ weeks PTO

Onsite Café & gym

Flexible work policy

Medical/Dental/Vision/401k

Charitable giving match

Job summary

Samsung Semiconductor's DRAM Development Lab in San Jose seeks a Principal Engineer for SOC design to advance memory/storage silicon solutions. You will drive architectural definitions, manage top-level integration, and coordinate with verification and physical-design teams to ensure a robust SoC.

The role demands deep ASIC experience, hands-on design flow knowledge, and strong collaboration across IP providers, architecture, and EDA tools in a fast-paced environment.

Qualifications

• Bachelor’s in Electrical or Computer Science or related with 20+ years experience, or Master’s with 18+, or PhD with 15+ years.
• Hands-on ASIC design flow from design to tape-out.
• Experience with UCIe, CPU, Ethernet, and DDR interfaces.
• Strong verbal and written communication skills.
• Self-motivated problem-solver and team player.

Responsibilities

• Participate in architectural definitions and micro-architecture of subsystem or chip level.
• Top integration, logic design and RTL implementation with quality checks.
• Reviews third-party IPs including ARM cores, DDR controller, and UCIe PHY.
• Integrate third-party IPs and subsystems at top level.
• Collaborate with architects and verification engineers for sound SoC design.
• Work with physical designers on timing, synthesis, DFT, and STA.

Skills

ASIC design flow

RTL design & verification

Timing analysis

ARM cores

AMBA bus fabric

DFT/PI/PD experience

Synthesis & CDC checks

Collaborative teamwork

Education

Bachelor's in Electrical/CS or related

Master's in Electrical/CS or related

PhD in Electrical/CS or related

Job description

Samsung Semiconductor's DRAM Development Lab in San Jose seeks a Principal Engineer for SOC design to advance memory/storage silicon solutions. You will drive architectural definitions, manage top-level integration, and coordinate with verification and physical-design teams to ensure a robust SoC.

The role demands deep ASIC experience, hands-on design flow knowledge, and strong collaboration across IP providers, architecture, and EDA tools in a fast-paced environment.