Senior SoC Physical Design Engineer - 7nm/5nm Lead

SK hynix memory solutions; Santa Clara (CA); On-site; USD 160,000 - 220,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Life insurance

401(k) match

Onsite gym

Cafeteria

Job summary

SK hynix memory solutions America Inc. is seeking a Sr. Staff Physical Design Engineer to lead high-performance SoC physical implementation from RTL to GDS. You will drive synthesis, placement, CTS, routing, and signoff while coordinating with front-end, DFT, power, and analog teams to optimize Power, Performance, and Area.

You will mentor junior engineers, define team methodologies, and contribute to tapeout schedules in a collaborative, onsite San Jose environment.

Qualifications

• BS/MS in Electrical or Computer Engineering or related field.
• 6+ years of hands-on ASIC physical design with tapeout experience.
• Expert-level proficiency with synthesis, placement, CTS, and routing tools.
• Deep knowledge of STA and PrimeTime signoff including multi-corner/multi-mode closure.
• Experience with Calibre DRC/LVS/ERC and IR drop/EM analysis.

Responsibilities

• Lead physical design implementation from synthesis through GDS for blocks or full-chip SoCs in advanced nodes (7nm, 5nm, 3nm).
• Drive timing closure and signoff; optimize PPA with cross-functional teams.
• Collaborate with front-end, DFT, power, and analog teams to ensure silicon success.
• Develop and maintain physical design flows and automation scripts; mentor juniors.

Skills

Synthesis

Placement

CTS

Routing

Timing closure

Mentoring

Leadership

Power integrity

Flow automation

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering

Master's preferred

Tools

Synopsys ICC2/Fusion Compiler

Cadence Innovus

PrimeTime

StarRC

Quantus

Calibre

Mentor Calibre

Ansys RedHawk

Tcl

Perl

Python

Job description

SK hynix memory solutions America Inc. is seeking a Sr. Staff Physical Design Engineer to lead high-performance SoC physical implementation from RTL to GDS. You will drive synthesis, placement, CTS, routing, and signoff while coordinating with front-end, DFT, power, and analog teams to optimize Power, Performance, and Area.

You will mentor junior engineers, define team methodologies, and contribute to tapeout schedules in a collaborative, onsite San Jose environment.