Lead Memory-Centric SoC Physical Design Engineer

Samsung Semiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

Onsite Café and gym

Flexible work environment

Comprehensive benefits

Job summary

Samsung Semiconductor in San Jose, CA seeks an experienced physical design engineer to own memory-centric IP and full-chip implementations from RTL to GDSII. You will drive PPA convergence, timing, and floorplanning for memory controllers, NoC, and high-speed interconnects, collaborating with RTL and verification teams.

The role requires strong scripting skills (Tcl/Python/Perl) and experience with AI/ML workloads, with a focus on delivering designs on time and within budget.

Qualifications

• Bachelor’s degree in EE/CS with 5+ years in physical design for ASIC/SoC.
• Advanced degree with hands-on ASIC/SoC experience is preferred.
• Proficiency with industry-standard EDA tools and hand-on experience in timing and power integrity.

Responsibilities

• Own the physical implementation of memory-centric computing IP and SoC partitions from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing.
• Drive block- and full-chip-level PPA convergence and timing closure across multiple process corners and operating modes.
• Develop floorplans, power delivery networks, and macro placement strategies for memory controllers, NoC, and high-bandwidth interconnect subsystems.
• Perform static timing analysis (STA), constraint development, and signoff, resolving setup/hold timing, IR-drop, electromigration, and signal integrity issues.
• Execute physical verification and signoff (DRC, LVS, antenna, and reliability checks) in collaboration with foundry and standard-cell/memory library teams on advanced process nodes.
• Collaborate with RTL and verification engineers, providing physical feedback that informs design-for-PPA and floorplan-aware microarchitecture decisions.
• Develop and automate physical implementation flows and methodologies using Tcl/Python scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the designs are delivered on time and within budget.
• Complete other responsibilities as assigned.

Skills

Memory-centric computing

RTL to GDSII flow

Synthesis/CTS/Place & Route

STA and timing closure

Python/Tcl scripting

AI/ML workloads

Collaboration & communication

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s in EE/CS

PhD in related field

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus

PrimeTime

StarRC

Job description

Samsung Semiconductor in San Jose, CA seeks an experienced physical design engineer to own memory-centric IP and full-chip implementations from RTL to GDSII. You will drive PPA convergence, timing, and floorplanning for memory controllers, NoC, and high-speed interconnects, collaborating with RTL and verification teams.

The role requires strong scripting skills (Tcl/Python/Perl) and experience with AI/ML workloads, with a focus on delivering designs on time and within budget.