Senior SOC Integration Engineer — Memory & AI

Conductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

Medical/Dental/Vision/401k health plan

Incentive opportunities

4+ weeks of paid time off

Fertility/adoption stipend

Job summary

Samsung Semiconductor’s DRAM Development Lab in San Jose seeks a Principal Engineer, SOC Integration to advance memory and storage technologies for cloud and data-center applications. You will lead integration of SoCs with high-speed interfaces, review IPs, and work with architects and verification teams to ensure robust, scalable system designs.

The role requires extensive experience in ASIC flow, SoC synthesis, timing, and IP integration, with a strong focus on AMBA, UCIe, DDR, and ARM cores.

Qualifications

• BS in Computer/Electrical Engineering or Computer Science with 20+ years of experience or MS with 18+ years of experience.
• Hands on knowledge & experience in ASIC design flow from design to tape out.
• Experience in commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.

Responsibilities

• Own the integration of SoCs with multiple high speed interfaces.
• Reviews 3 rd party IPs including ARM cores, DDR controller, and UCIe PHY.
• Responsible for integrating third party IPs with system bus, peripherals and CPU cores.
• Work with architects and verification engineers to ensure sound design at SoC level.
• Collaborate with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.

Skills

ASIC design flow

AMBA bus fabric

ARM CPU cores

DDR interfaces

UCIe IPs

SoC integration

Education

BS in Computer/Electrical Engineering or Computer Science

MS in Computer Science/Engineering

Job description

Samsung Semiconductor’s DRAM Development Lab in San Jose seeks a Principal Engineer, SOC Integration to advance memory and storage technologies for cloud and data-center applications. You will lead integration of SoCs with high-speed interfaces, review IPs, and work with architects and verification teams to ensure robust, scalable system designs.

The role requires extensive experience in ASIC flow, SoC synthesis, timing, and IP integration, with a strong focus on AMBA, UCIe, DDR, and ARM cores.