Senior SoC Design Architect for Next-Gen Memory

Samsung Semiconductor Inc.; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Job summary

Samsung Semiconductor's DRAM Development Lab in the Silicon Valley is seeking a Principal Engineer to help design next-generation SOCs. You will participate in architectural definitions, manage top-level integration, and work with ARM cores, IPs, and memory controllers to push performance and efficiency.

You’ll collaborate with architects, verification and physical designers, addressing timing, synthesis, DFT, and CDC while leading top-level design efforts and contributing to tape-out readiness.

Qualifications

• 5+ years of experience in ASIC/SoC design or a PhD with substantial industry experience.
• Strong knowledge of memory controllers, UCIe/IPs, and ARM cores.
• Hands-on experience from design to tape-out including DFT/PD/PI.
• Experienced with timing, synthesis, lint, CDC checks and STA.

Responsibilities

• Participate in architectural definitions and micro-architecture at subsystem or chip level.
• Lead top integration, logic design, RTL implementation with quality checks.
• Review third-party IPs including ARM cores and DDR controllers.
• Integrate third-party IPs and subsystems at top level with your team.
• Collaborate with architects and verification engineers for sound SoC design.
• Coordinate with physical designers on timing, synthesis, DFT/CDC/STA.

Skills

ASIC design

RTL implementation

SoC integration

DFT/PI/PD interfacing

AMBA bus fabric

ARM cores

UCIe IPs

DDR interfaces

Timing analysis

Synthesis

CDC checks

3rd party IP reviews

Education

Bachelor's in Electrical or Computer Science

Master's in Electrical or Computer Science

PhD in Electrical or Computer Science

Tools

ARM cores

UCIe

DDR controller

Job description

Samsung Semiconductor's DRAM Development Lab in the Silicon Valley is seeking a Principal Engineer to help design next-generation SOCs. You will participate in architectural definitions, manage top-level integration, and work with ARM cores, IPs, and memory controllers to push performance and efficiency.

You’ll collaborate with architects, verification and physical designers, addressing timing, synthesis, DFT, and CDC while leading top-level design efforts and contributing to tape-out readiness.