Senior Physical Design Engineer – GF 12LP, Remote in USA

Encore Semi, Inc.; Boston (MA); À distance; USD 135 000 - 165 000; Plein temps

Avantages offerts par ce poste

15 days PTO

10 holidays/year

Medical benefits 80% premiums

Dental & Vision 50% premiums

Life Insurance & Disability

Tuition reimbursement

EAP

401k (Traditional & Roth)

Résumé du poste

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs on GF 12LP, driving robust timing closure and PPA optimization.

The role demands ownership of advanced FinFET challenges and a proactive approach to automation using Tcl and Python. You will work remotely from anywhere in the USA, collaborating with teams to deliver tape-outs and ensure design integrity from synthesis to signoff, with competitive compensation and

Qualifications

• 5+ years of ASIC physical design with proven tape-outs on FinFET nodes (≤14nm/12nm)
• Experience with Synopsys Fusion Compiler and PrimeTime
• Strong grounding in synthesis, CTS, complex SDC constraints, and signoff methodologies
• Scripting in Tcl, Python, or Perl
• BS or MS in EE/CE or a related field

Responsabilités

• Drive block- and top-level physical design from synthesis through GDSII signoff using the Fusion Design Platform
• Execute floorplanning, power grid design, placement, CTS, and routing for GF 12LP architectures
• Lead STA, parasitic extraction, and multi-corner/multi-mode closure using PrimeTime and StarRC
• Address FinFET challenges, including DRC/LVS and EM/IR-drop analysis
• Develop Tcl and Python scripts to streamline flows and track PPA metrics

Connaissances

ASIC Physical Design

Fusion Compiler

PrimeTime

Tcl/Python/Perl

Synthesis & CTS

Formation

BS or MS in Electrical/Computer Engineering

Outils

Synopsys Fusion Compiler

PrimeTime

RedHawk / EM analysis

Description du poste

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs on GF 12LP, driving robust timing closure and PPA optimization.

The role demands ownership of advanced FinFET challenges and a proactive approach to automation using Tcl and Python. You will work remotely from anywhere in the USA, collaborating with teams to deliver tape-outs and ensure design integrity from synthesis to signoff, with competitive compensation and