Senior Physical Design Engineer for AI-Driven Silicon

Advanced Micro Devices, Inc.; Santa Clara (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Advanced Micro Devices, Inc. seeks a hands-on physical design expert to lead advanced-node ASIC/SoC implementations. You will drive timing closure, ECO strategies, and PPA optimization while collaborating with architecture, RTL, CAD, and product teams to deliver high-quality silicon.

You will mentor engineers, pushautomation, and contribute to data-driven design workflows, enabling scalable solutions in a fast-paced environment.

Qualifications

• Experience in ASIC physical design, implementation, and timing closure.
• Experience across block, subsystem, and chip-level design environments.
• Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
• Proficiency with industry-standard tools such as ICC2, Fusion Compiler and/or Innovus.
• Experience with timing, power and signoff tools (e.g., PrimeTime, PrimeTime PX, PrimeShield).
• Advanced-node semiconductor design with leading-edge processes.
• Strong scripting skills (TCL, Python, Perl).
• Exposure to ML or data-driven design optimization workflows.

Responsibilities

• Lead physical design activities across block, subsystem, and chip-level implementations.
• Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
• Develop and enhance physical design methodologies, flows, and automation.
• Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
• Define and execute ECO strategies throughout implementation and signoff.
• Support formal verification, physical verification, and tapeout prep activities.
• Analyze design data to improve quality, predictability, and efficiency.
• Collaborate with cross-functional teams to deliver silicon successfully.
• Contribute to AI-assisted design optimization initiatives.
• Troubleshoot complex implementation challenges and develop scalable solutions.

Skills

ASIC physical design

Timing closure

Static timing analysis

Scripting automation

Cross-functional collaboration

Mentoring

Data-driven optimization

LDK/SoC integration

Education

Bachelor's or Master's degree in Electrical/Computer Engineering or related field

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime/PrimeTime PX

PrimeShield

RedHawk

Formality

Conformal

Job description

Advanced Micro Devices, Inc. seeks a hands-on physical design expert to lead advanced-node ASIC/SoC implementations. You will drive timing closure, ECO strategies, and PPA optimization while collaborating with architecture, RTL, CAD, and product teams to deliver high-quality silicon.

You will mentor engineers, pushautomation, and contribute to data-driven design workflows, enabling scalable solutions in a fast-paced environment.