Lead AI/SoC Physical Design Engineer

AMD; Santa Clara (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

AMD is seeking a hands-on physical design expert to lead and contribute to advanced-node ASIC/SoC implementations. You will drive timing closure, signoff readiness, and PPA optimization across block, subsystem, and chip levels while refining design methodologies and automation.

Collaboration with architecture, RTL, CAD, and product teams is essential. The role demands leadership, deep technical expertise, and the ability to mentor engineers across globally distributed teams in a fast-paced

Qualifications

• Experience with ASIC physical design and timing closure.
• Experience across block, subsystem, and chip-level design environments.
• Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.

Responsibilities

• Lead physical design activities across block, subsystem, and chip-level implementations.
• Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
• Develop and enhance physical design methodologies, flows, and automation.
• Perform static timing analysis and clock-tree optimization.
• Define and execute ECO strategies throughout implementation and signoff.
• Support formal verification, physical verification, and tapeout preparation.
• Analyze design data to improve quality, predictability, and efficiency.
• Collaborate with cross-functional teams to deliver silicon on schedule.
• Contribute to AI-assisted design optimization initiatives.

Skills

ASIC physical design

Timing closure

PPA optimization

Scripting TCL/Python

EDA tools knowledge

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's degree preferred

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime/PrimeTime PX

RedHawk/Formality/Conformal

Job description

AMD is seeking a hands-on physical design expert to lead and contribute to advanced-node ASIC/SoC implementations. You will drive timing closure, signoff readiness, and PPA optimization across block, subsystem, and chip levels while refining design methodologies and automation.

Collaboration with architecture, RTL, CAD, and product teams is essential. The role demands leadership, deep technical expertise, and the ability to mentor engineers across globally distributed teams in a fast-paced