Senior Physical Design Engineer for AI Accelerator SoCs

River AI; Palo Alto (CA); On-site; USD 200,000 - 420,000; Full time

Job summary

River AI seeks exceptional physical design engineers to transform architectural concepts into production-ready silicon. You will own the physical flow from RTL synthesis through tape-out, pushing limits of advanced foundry nodes to maximize PPA for our AI accelerator.

You will collaborate with RTL/architecture teams to close timing, electrical, and physical verification, while driving design closure and automation across the flow. Based in Austin or Palo Alto with competitive compensation.

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering is required.
• 5+ years experience with advanced process nodes (7nm or below).
• Experience with physical design tools and sign-off workflows.
• Strong debugging and trade-off skills in timing, congestion, and power density.

Responsibilities

• Own the physical implementation flow from RTL synthesis through placement, CTS, and routing for high-performance blocks.
• Maximize cell density and PDN robustness to meet aggressive frequency targets on advanced nodes.
• Close timing, electrical violations, and SI/EM/IR-drop constraints across clock domains.
• Run sign-off physical verification (DRC, LVS, Antenna) and fix issues.
• Co-design with RTL to provide early physical feedback on logic structures and routing congestion.
• Advance flow automation by integrating AI-driven EDA tools and workflow pipelines.

Skills

5+ years exp

Debugging skills

Collaboration

RTL co-design

Education

Bachelor’s degree in Electrical or Computer Engineering

Tools

Innovus

Fusion Compiler

PrimeTime

RedHawk

Job description

River AI seeks exceptional physical design engineers to transform architectural concepts into production-ready silicon. You will own the physical flow from RTL synthesis through tape-out, pushing limits of advanced foundry nodes to maximize PPA for our AI accelerator.

You will collaborate with RTL/architecture teams to close timing, electrical, and physical verification, while driving design closure and automation across the flow. Based in Austin or Palo Alto with competitive compensation.