Sr. Physical Design Engineer

Advanced Micro Devices, Inc.; Santa Clara (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Advanced Micro Devices, Inc. seeks a hands-on physical design expert to lead advanced-node ASIC/SoC implementations. You will drive timing closure, ECO strategies, and PPA optimization while collaborating with architecture, RTL, CAD, and product teams to deliver high-quality silicon.

You will mentor engineers, pushautomation, and contribute to data-driven design workflows, enabling scalable solutions in a fast-paced environment.

Qualifications

• Experience in ASIC physical design, implementation, and timing closure.
• Experience across block, subsystem, and chip-level design environments.
• Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
• Proficiency with industry-standard tools such as ICC2, Fusion Compiler and/or Innovus.
• Experience with timing, power and signoff tools (e.g., PrimeTime, PrimeTime PX, PrimeShield).
• Advanced-node semiconductor design with leading-edge processes.
• Strong scripting skills (TCL, Python, Perl).
• Exposure to ML or data-driven design optimization workflows.

Responsibilities

• Lead physical design activities across block, subsystem, and chip-level implementations.
• Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
• Develop and enhance physical design methodologies, flows, and automation.
• Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
• Define and execute ECO strategies throughout implementation and signoff.
• Support formal verification, physical verification, and tapeout prep activities.
• Analyze design data to improve quality, predictability, and efficiency.
• Collaborate with cross-functional teams to deliver silicon successfully.
• Contribute to AI-assisted design optimization initiatives.
• Troubleshoot complex implementation challenges and develop scalable solutions.

Skills

ASIC physical design

Timing closure

Static timing analysis

Scripting automation

Cross-functional collaboration

Mentoring

Data-driven optimization

LDK/SoC integration

Education

Bachelor's or Master's degree in Electrical/Computer Engineering or related field

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime/PrimeTime PX

PrimeShield

RedHawk

Formality

Conformal

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou'redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger- technologythat moves the world forward.Join us and, together, we'll advance your career.

THE ROLE:

Join a team developing next-generation AI and high-performance computing silicon. In this role, you will lead and contribute to advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff, and design optimization across block, subsystem, and chip-level designs. Working closely with architecture, RTL, CAD, technology, and product engineering teams, you will help deliver high-quality silicon while advancing methodology, automation, and data-driven design solutions that improve power, performance, and area (PPA).

THE PERSON:

You are a hands-on physical design expert with a strong track record of solving complex implementation and timing challenges on advanced-node designs. You combine deep technical expertise with the ability to provide technical leadership, influence design decisions, mentor engineers, and collaborate effectively across globally distributed teams. You are detail-oriented, highly analytical, and thrive in fast-paced environments where ownership and innovation are valued.

KEY RESPONSIBLITIES:

• Lead physical design activities across block, subsystem, and chip-level implementations.
• Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
• Develop and enhance physical design methodologies, design flows, and automation solutions.
• Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
• Define and execute engineering change (ECO) strategies throughout implementation and signoff.
• Support formal verification, physical verification, and tapeout preparation activities.
• Analyze design data and trends to improve design quality, predictability, and efficiency.
• Collaborate with cross-functional engineering teams to achieve successful silicon delivery.
• Contribute to AI-assisted and machine learning-driven design optimization initiatives.
• Troubleshoot complex implementation challenges and develop scalable technical solutions.

PREFERRED EXPERIENCE:

• Experience with ASIC physical design, implementation, and timing closure.
• Experience working across block, subsystem, and chip-level design environments.
• Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
• Experience with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, and/or Cadence Innovus.
• Experience with timing, power, and signoff tools such as PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, or Conformal.
• Advanced-node semiconductor design experience, including leading-edge process technologies.
• Strong scripting and automation skills using TCL, Python, Perl, Pandas, or similar technologies.
• Experience developing design flows, methodologies, and productivity-enhancing automation.
• Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows.
• Experience with data analysis, database technologies, and design-quality metrics.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.

This role is not eligible for visa sponsorship.

#LI-LC3

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.