Senior Physical Design Lead: High-Impact ASIC Programs

CyberCoders; San Jose (CA); On-site; USD 500,000 - 800,000; Full time

Job summary

CyberCoders in Silicon Valley, CA seeks Principal and Master Physical Design Engineering Leads to guide customer ASIC programs and deliver highly complex designs. This senior level role is hands-on (about 80%) with some technical leadership to drive outcomes for AI and HPC projects.

You will coordinate end-to-end tapeouts, optimize PPA, and collaborate with EDA teams. The role emphasizes deep physical design expertise, advanced node flows, and clear communication across customers and internal

Qualifications

• Hands-on experience in physical design or STA, with EDA tools and flows.
• Multiple tape-outs at advanced process nodes.
• Ability to analyze PPA tradeoffs across library components, architectures, and implementation strategies.
• Thorough understanding of low power design techniques and power management.
• Programming or scripting experience.
• Excellent communication skills.

Responsibilities

• Driving end-to-end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring-up, and production.
• Managing physical design validation flows to ensure incoming customer netlists meet strict tape-out quality requirements.
• Hosting informative sessions with technical experts and advising customer teams on EDA best practices, design flows, and methodologies.
• Identifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teams.

Skills

Hands-on physical design/STA

Multiple tape-outs

PPA tradeoffs analysis

Low power design techniques

Programming/scripting

Excellent communication

Tools

EDA tools

Job description

CyberCoders in Silicon Valley, CA seeks Principal and Master Physical Design Engineering Leads to guide customer ASIC programs and deliver highly complex designs. This senior level role is hands-on (about 80%) with some technical leadership to drive outcomes for AI and HPC projects.

You will coordinate end-to-end tapeouts, optimize PPA, and collaborate with EDA teams. The role emphasizes deep physical design expertise, advanced node flows, and clear communication across customers and internal