Senior Physical Design Engineer – AI/High-Speed ASICs

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity awards

Comprehensive benefits

Job summary

Broadcom in San Jose, CA is seeking a Senior Physical Design Engineer to drive the RTL-to-tapeout flow for advanced AI and PCIe switch products within the APD ASIC group. You will own block- and top-level implementations using Cadence Innovus and collaborate across design, verification, and foundry teams.

Responsibilities include floorplanning, placement, CTS, routing, timing and power optimization on 5nm/3nm nodes, plus signoff preparation with PrimeTime, StarRC, and Calibre.

Qualifications

• Bachelor's or master's degree in electrical or computer engineering or related field.
• 8+ years of hands-on physical design and tapeout experience.
• Experience with advanced nodes (N7/N5/N3) and foundry processes.
• Strong TCL, Python, and Unix scripting for flow automation.

Responsibilities

• Lead block-level and top-level implementation from floorplanning to GDSII stream-out.
• Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced nodes.
• Perform MCMM STA, SI optimization, and IR/EM-aware signoff using PrimeTime, Voltus, or RedHawk.

Job description

Broadcom in San Jose, CA is seeking a Senior Physical Design Engineer to drive the RTL-to-tapeout flow for advanced AI and PCIe switch products within the APD ASIC group. You will own block- and top-level implementations using Cadence Innovus and collaborate across design, verification, and foundry teams.

Responsibilities include floorplanning, placement, CTS, routing, timing and power optimization on 5nm/3nm nodes, plus signoff preparation with PrimeTime, StarRC, and Calibre.