Senior ASIC Floorplanning Engineer – Top-Level PD (Onsite)

Broadcom Inc.; San Jose (CA); On-site; USD 121,900 - 195,000; Full time

Job summary

Broadcom Inc. is seeking an ASIC top-level floorplan Physical Design Engineer to join the ASIC Products Division in San Jose.

You will own floorplanning, clocking and I/O planning for top-level partitions, collaborating with design, package and methodology teams to deliver silicon tape-out. The role requires deep experience in die size estimation, partitioning and DRC/LVS resolution for advanced nodes, plus scripting skills (Python/Tcl/Perl) and hands-on use of EDA tools.

Qualifications

• Bachelor’s degree plus 8+ years in top-level floorplanning with die size estimate, partitioning, clocking and pin planning
• Or Master’s degree with 6+ years in top-level floorplanning with die size estimate, partitioning, clocking and pin planning
• Experience with Switch Fabric, Arbiter, High-Speed DDR, SerDes, HBM, D2D I/O, chiplet, etc.
• Experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes
• Proven track record with bump planning, RDL implementation, and multi-voltage domain designs
• Experience with hierarchical floorplanning, power grid design, structured clocks, top-level pipeline planning, custom routes and bump planning
• Experience collaborating with design, package and methodology teams during development
• Must work in person at our San Jose site – no remote work option

Responsibilities

• Own chip floor planning, partition creation, clock tree and delivery of top-level partitions
• Resolve physical design issues related to chip integration and assembly
• Manage all cross-functional interactions related to top-level floorplanning, I/O and bump planning with package team
• Develop and improve floorplan implementation methodologies using both industry and internal tools
• Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specifications

Skills

Floorplanning

Clocking

Pin planning

Python

Tcl

Perl

EDA tools

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

EDA tools

Job description

Broadcom Inc. is seeking an ASIC top-level floorplan Physical Design Engineer to join the ASIC Products Division in San Jose.

You will own floorplanning, clocking and I/O planning for top-level partitions, collaborating with design, package and methodology teams to deliver silicon tape-out. The role requires deep experience in die size estimation, partitioning and DRC/LVS resolution for advanced nodes, plus scripting skills (Python/Tcl/Perl) and hands-on use of EDA tools.