Senior Physical Verification Engineer - Onsite San Jose

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom’s ASIC Products Division seeks a Principal Physical Design Engineer to drive physical verification for next‑gen AI/ML and PCIe Switch projects. Based in San Jose, you will guide DRM runsets, floorplan rules, and chip‑level repair strategies while leading complex tapeouts and DFM improvements.

You will collaborate with design and CAD teams, applying LVS/DRC/ERC/PERC expertise, scripting skills, and robust communication to deliver high‑yield silicon and first‑pass success.

Qualifications

• Hands-on experience in running physical verification (LVS, DRC, ERC, PERC).
• Experience with EDA tools and flows such as ICV, Calibre and Pegasus EDA tools.
• Rule deck coding experience in ICV, Calibre or Pegasus EDA tools.
• Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience.
• Electrical Rule Checking (ERC/PERC): Analyze ESD, latch‑up, floating gates, and power‑domain isolation vulnerabilities.
• Density & Fill: Manage automated dummy metal, poly, and diffusion filling strategies to meet density rules.
• Yield Enhancement (DFM): Implement fixes including CAA, via‑doubling, edge displacement rules.
• Collaborate with physical design to resolve top‑level integration bottlenecks.
• Experience in scripting languages like Python, Tcl, or Perl
• Excellent verbal and written communication skills
• Must work in person at our San Jose site and no remote work allowed

Responsibilities

• Execution of Chip level Physical Verification & Issue resolution
• Work on setting up DRM runsets for advance nodes and tool flows
• Manage and guide rules related to Top level Floorplan, I/O and bump planning
• Resolve physical design issues related to chip integration and assembly
• Provide technical direction on verification methodologies including DRC, LVS, ERC, and PERC
• Develop best practice guidelines for physical verification flows and runtime optimizations

Skills

Hands-on verification

Experience with foundry rules

Scripting (Python, Tcl, Perl)

Strong communication skills

Team collaboration

Education

Bachelor’s degree in Electrical or Electronics Engineering

Tools

ICV

Calibre

Pegasus EDA

Job description

Broadcom’s ASIC Products Division seeks a Principal Physical Design Engineer to drive physical verification for next‑gen AI/ML and PCIe Switch projects. Based in San Jose, you will guide DRM runsets, floorplan rules, and chip‑level repair strategies while leading complex tapeouts and DFM improvements.

You will collaborate with design and CAD teams, applying LVS/DRC/ERC/PERC expertise, scripting skills, and robust communication to deliver high‑yield silicon and first‑pass success.