Senior Physical Verification Engineer, ASIC (3nm/2nm)

Broadcom Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

Medical, dental and vision plans

401(K) with company matching

ESPP

Paid holidays

Job summary

Broadcom's APD division seeks a Principal Physical Design Engineer to lead chip-level physical design and verification for advanced ASICs. This role requires hands-on verification, deep PD knowledge, and on-site collaboration at the San Jose campus.

You will work on 3nm/2nm nodes, drive floorplanning, DRC/LVS/PERC, and provide scripting-based flow improvements, with strong communication across teams.

Qualifications

• Bachelor's degree in Electrical or Electronics Engineering
• 12+ years of relevant experience in ASIC physical design
• Hands-on physical verification experience (LVS, DRC, ERC, PERC)
• Experience with 3nm/2nm nodes and chip integration
• Must work in San Jose site; on-site only
• Strong scripting (Python, Tcl, or Perl)

Responsibilities

• Execute chip-level physical verification and resolve issues
• Set up DRM runsets for advanced nodes and tool flows
• Manage rules for top-level floorplan, I/O and bump planning
• Resolve physical design issues related to chip integration and assembly
• Provide technical direction on verification methodologies (DRC/LVS/ERC/PERC)
• Develop best-practice guidelines for verification flows and optimizations

Skills

Physical verification

LVS DRC ERC PERC

EDA tools

Calibre Pegasus ICV

Python scripting

Top-level floorplan

Communication

On-site only

Tape-out experience

Density & Fill

Education

Bachelor's degree in Electrical or Electronics Engineering

Tools

Calibre

Pegasus

ICV

Job description

Broadcom's APD division seeks a Principal Physical Design Engineer to lead chip-level physical design and verification for advanced ASICs. This role requires hands-on verification, deep PD knowledge, and on-site collaboration at the San Jose campus.

You will work on 3nm/2nm nodes, drive floorplanning, DRC/LVS/PERC, and provide scripting-based flow improvements, with strong communication across teams.