Senior Package Architect: Silicon-to-System Co-Design

Micron Technology, Inc.; Boise (ID); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology seeks a Senior Package Design Engineer to lead cross‑functional packaging from silicon to system to high‑volume manufacturing. You’ll shape DRAM packaging across AI/data center applications, partnering with silicon teams and OSATs to deliver scalable, reliable solutions.

You will drive die floorplan optimization, substrate stack‑ups, and BEOL/RDL flows, while coordinating with SI/PI teams to ensure robust designs and manufacturability at scale.

Qualifications

• Bachelor's degree in Electrical, Mechanical, Materials Science or related field with 5+ years' package design experience.
• Or Master's degree with 3+ years' experience in semiconductor package design.
• Hands-on proficiency with advanced package EDA tools and interconnects.

Responsibilities

• Lead Co-Design from Silicon to System from early-stage to High Volume Manufacturing.
• Optimize die floorplans, interconnects, and package architectures end-to-end.
• Drive trade-off studies for DRAM products targeting AI, data center, mobile, and edge.
• Own package layout, high-density routing, placement, and substrate stack-ups.
• Define BEOL/RDL flows, wire bonds, and interconnect schemes.
• Create wiring diagrams and manufacturing documentation for production.
• Collaborate with SI/PI teams, OSAT partners, and design teams to optimize designs.

Skills

Package design

EDA tools

Chip-to-package co-design

OSAT collaboration

Education

Bachelor's in Electrical/Mechanical/Materials Science or related

Master's in Electrical/Mechanical/Materials Science or related

Tools

Cadence Allegro Package Designer+

Cadence Integrity 3D-IC

Siemens/Mentor Xpedition

AutoCAD / Autodesk Mechanical

Job description

Micron Technology seeks a Senior Package Design Engineer to lead cross‑functional packaging from silicon to system to high‑volume manufacturing. You’ll shape DRAM packaging across AI/data center applications, partnering with silicon teams and OSATs to deliver scalable, reliable solutions.

You will drive die floorplan optimization, substrate stack‑ups, and BEOL/RDL flows, while coordinating with SI/PI teams to ensure robust designs and manufacturability at scale.