Lead Silicon Packaging Architect

Intel; Phoenix (AZ); Hybrid; USD 191,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel is seeking a Silicon Packaging Architect to design end-to-end package solutions meeting electrical, mechanical, thermal and cost targets. You will oversee design through production readiness, working with silicon, hardware and manufacturing teams to enable tape-out readiness in a hybrid work model.

Qualified candidates bring 9+ years in semiconductor packaging or a related field, strong DFM/DOE expertise, and proven ability to lead cross-functional efforts across US locations, including

Qualifications

• Bachelor's degree in ME/EE/Materials Science or related field with 9+ years of hands-on experience
• 4+ years of experience defining semiconductor/electronic package architectures
• Experience applying Design for Manufacturing (DFM) principles
• Utilizing Design of Experiments (DOE) methodologies
• Troubleshooting package design and manufacturing issues

Responsibilities

• Translate product requirements into detailed package architecture specifications.
• Lead technology trade-off decisions ensuring packaging solutions meet electrical, mechanical, thermal, and reliability standards.
• Collaborate with silicon, hardware, and package leads to deliver high-quality package outputs and address roadblocks.
• Oversee the packaging development process, including design, processes, and procedures, while driving continuous improvement in packaging quality standards.
• Apply expertise in troubleshooting package designs, resolving technical issues, and delivering innovative, cost-effective solutions.
• Partner with manufacturing teams to ensure seamless design-to-production transitions and support tape-out readiness.
• Utilize Design for Manufacturing (DFM) principles to optimize package designs for manufacturability and production efficiency.
• Maintain and refine technical documentation to support package development processes.

Skills

Package architecture design

Cross-functional collaboration

DOE methodologies

Design for Manufacturing

Troubleshooting

Technical documentation

Education

Bachelor's degree in Mechanical Engineering, Electrical Engineering, Materials Science or related field

Master's degree in a relevant field

PhD in a relevant field

Tools

DFM

DOE

Job description

Intel is seeking a Silicon Packaging Architect to design end-to-end package solutions meeting electrical, mechanical, thermal and cost targets. You will oversee design through production readiness, working with silicon, hardware and manufacturing teams to enable tape-out readiness in a hybrid work model.

Qualified candidates bring 9+ years in semiconductor packaging or a related field, strong DFM/DOE expertise, and proven ability to lead cross-functional efforts across US locations, including