Senior Package Layout Engineer: High-Speed ASICs & Equity

NVIDIA; North Carolina; On-site; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Package Layout Engineer to join our layout team to design high-speed, high-density ASIC packages and substrates. You will collaborate to implement advanced layouts and optimize package pinouts with system-level trade-offs.

You will use Cadence APD or SiP tool suites, develop CAD libraries, and contribute to design feasibility studies while advancing layout productivity. Equity and benefits are offered. Base salary ranges from USD 108,000 to USD 184,000.

Qualifications

• Hold a B.S. Electrical Engineering or equivalent experience.
• 2+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology.
• Experience with HDI designs is a plus.
• Proven experience in substrate layout of wire bond and flip chip packages, preferred.
• Solid understanding of high-speed design signal integrity practices.

Responsibilities

• Collaborate to implement high speed/density ASIC packages.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pinout incorporating system level trade-offs of pins assignment.
• Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.
• Propose layout design trade-offs to the Technical Package Lead for resolution and implementation.
• Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance.
• Develop symbols and CAD library databases using Cadence APD design tools
• Develop methodologies to improve layout productivity

Skills

High-speed design

Education

B.S. Electrical Engineering or equivalent experience

Tools

Cadence APD

SiP

Constraint Manager

Virtuoso

Calibre

Valor

Job description

NVIDIA is seeking a Senior Package Layout Engineer to join our layout team to design high-speed, high-density ASIC packages and substrates. You will collaborate to implement advanced layouts and optimize package pinouts with system-level trade-offs.

You will use Cadence APD or SiP tool suites, develop CAD libraries, and contribute to design feasibility studies while advancing layout productivity. Equity and benefits are offered. Base salary ranges from USD 108,000 to USD 184,000.