Senior Package Layout Engineer – Hybrid with Equity Options

NVIDIA Corporation

Santa Clara (CA)

Hybrid

USD 136,000 - 259,000

Full time

14 days+

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Benefits offered by this job

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Benefits

Job summary

NVIDIA Corporation in Santa Clara, California seeks a Senior Package Layout Engineer to contribute to high-speed, high-density IC substrate layouts for NVIDIA products. You will collaborate with the Technical Package Lead and design teams to plan schedules, optimize pinouts, routing, stack-up, power distribution, and trade-offs using Cadence APD/SIP tools.

BS in Electrical Engineering and 5+ years PCB layout for GPUs or similar; wire-bond/flip-chip substrate experience and signal integrity

Qualifications

  • BS in Electrical Engineering required.
  • 5+ years PCB layout experience for GPUs or related tech.
  • Substrate layout of wire-bond and flip-chip packages preferred.
  • Cadence APD or SiP and PCB layout tools experience.
  • Strong understanding of high-speed design and signal integrity.
  • Experience with Virtuoso, Calibre, and Valor is a plus.

Responsibilities

  • Implement high-speed/density ASIC package layouts.
  • Produce substrate breakout patterns for ASIC packages.
  • Optimize package pinouts with system-level trade-offs.
  • Assist in package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tools.
  • Propose layout design trade-offs to the Technical Package Lead.
  • Conduct feasibility studies on package design goals (size, cost, performance).
  • Develop CAD library symbols and databases; improve layout productivity.

Skills

High-speed design
Signal integrity
HDI knowledge
Collaboration
Layout optimization

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence APD
SiP
PCB Layout Tools
Constraint Manager
Virtuoso
Calibre
Valor

Job description

NVIDIA Corporation in Santa Clara, California seeks a Senior Package Layout Engineer to contribute to high-speed, high-density IC substrate layouts for NVIDIA products. You will collaborate with the Technical Package Lead and design teams to plan schedules, optimize pinouts, routing, stack-up, power distribution, and trade-offs using Cadence APD/SIP tools.

BS in Electrical Engineering and 5+ years PCB layout for GPUs or similar; wire-bond/flip-chip substrate experience and signal integrity

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