Senior Package Layout Engineer – High-Speed GPU Hardware

NVIDIA; Arizona; On-site; USD 108,000 - 184,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Package Layout Engineer to advance high-speed ASIC package layouts for GPUs and related products. The role emphasizes HDI-aware substrate layouts, wire-bond/flip-chip considerations, and tight signal integrity practices.

You will collaborate within a layout team to optimize pinouts, routing, and power distribution, leveraging Cadence APD and related tools. Equity and benefits accompany this full-time position in the United States.

Qualifications

• BS in Electrical Engineering or equivalent experience.
• 2+ years in PCB layout for graphics cards, motherboards, line cards or related tech; HDI is a plus.
• Substrate layout of wire-bond and flip-chip packages preferred.
• Strong background with high-speed design signal integrity practices.

Responsibilities

• Collaborate to implement high speed/density ASIC packages.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pinout with system-level trade-offs of pins assignment.
• Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.
• Propose layout design trade-offs to the Technical Package Lead for resolution and implementation.
• Conduct design feasibility studies to evaluate size, cost, and system performance goals.
• Develop symbols and CAD library databases using Cadence APD design tools
• Develop methodologies to improve layout productivity

Skills

Signal integrity understanding

PCB layout

Team collaboration

Education

B.S. Electrical Engineering

Tools

Cadence APD

Constraint Manager

Virtuoso

Calibre

Valor

SiP toolset

PCB layout tools

Job description

NVIDIA is seeking a Senior Package Layout Engineer to advance high-speed ASIC package layouts for GPUs and related products. The role emphasizes HDI-aware substrate layouts, wire-bond/flip-chip considerations, and tight signal integrity practices.

You will collaborate within a layout team to optimize pinouts, routing, and power distribution, leveraging Cadence APD and related tools. Equity and benefits accompany this full-time position in the United States.