Senior Package Layout Engineer, High-Speed ASICs

NVIDIA Corporation; Santa Clara (CA); Hybride; USD 108 000 - 184 000; Plein temps

Résumé du poste

NVIDIA is seeking a Senior Package Layout Engineer in Santa Clara, CA to design high-speed, high-density ASIC packages. You will collaborate with the Technical Package Lead and design teams to develop substrate layout, routing, and power distribution using Cadence APD or SiP tools.

The ideal candidate has a BS in Electrical Engineering, 2+ years in PCB layout for graphics cards or related tech, and experience with HDI, wire-bond/flip-chip substrates, and SI practices.

Qualifications

• Hold a B.S. Electrical Engineering or equivalent experience.
• 2+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology.
• Experience with HDI designs is a plus.
• Proven experience in substrate layout of wire bond and flip chip packages, preferred.
• Solid understanding of high-speed design signal integrity practices.
• Experience with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager).
• Experience using Valor is helpful.

Responsabilités

• Collaborate to implement high speed/density ASIC packages.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pinout incorporating system level trade-offs of pins assignment.
• Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.
• Propose layout design trade-offs to the Technical Package Lead for resolution and implementation.
• Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance.
• Develop symbols and CAD library databases using Cadence APD design tools
• Develop methodologies to improve layout productivity

Connaissances

PCB Layout

Signal Integrity

HDI Designs

Wire Bond/Flip Chip Substrates

Formation

B.S. Electrical Engineering

Outils

Cadence APD

SiP Tools

Virtuoso

Calibre

Valor

Description du poste

NVIDIA is seeking a Senior Package Layout Engineer in Santa Clara, CA to design high-speed, high-density ASIC packages. You will collaborate with the Technical Package Lead and design teams to develop substrate layout, routing, and power distribution using Cadence APD or SiP tools.

The ideal candidate has a BS in Electrical Engineering, 2+ years in PCB layout for graphics cards or related tech, and experience with HDI, wire-bond/flip-chip substrates, and SI practices.