Senior IC Substrate & High-Speed Layout Engineer

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 259,000; Full time

Job summary

NVIDIA Corporation is seeking a Senior Package Layout Engineer in Santa Clara, CA, to design intricate IC substrate layouts for graphics products. You will collaborate with design teams to optimize size, cost, and performance across high-speed substrates.

You will work with Cadence APD/SiP tools, develop CAD libraries, and drive layout decisions to meet stringent engineering goals in a hybrid work environment.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent with 5+ years PCB layout experience.

Responsibilities

• Collaborate to implement high speed/density ASIC package layouts.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pinout with system-level trade-offs.
• Contribute to package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.
• Propose layout trade-offs to Technical Package Lead and implement.
• Conduct design feasibility studies for size, cost, and system performance.
• Develop symbols and CAD library databases using Cadence APD design tools.
• Develop methodologies to improve layout productivity.

Skills

High-speed PCB layout

Cadence tools

APD/SiP design

PCB topologies

Signal integrity

Virtuoso

Calibre

Valor

Education

B.S. Electrical Engineering

Tools

Cadence APD

SiP tooling

Job description

NVIDIA Corporation is seeking a Senior Package Layout Engineer in Santa Clara, CA, to design intricate IC substrate layouts for graphics products. You will collaborate with design teams to optimize size, cost, and performance across high-speed substrates.

You will work with Cadence APD/SiP tools, develop CAD libraries, and drive layout decisions to meet stringent engineering goals in a hybrid work environment.