Senior Package Layout Engineer for GPU Hardware (Equity)

NVIDIA Corporation; California; On-site; USD 136,000 - 259,000; Full time

Job summary

NVIDIA is seeking a Senior Package Layout Engineer in California to join the Layout team. You will implement high-speed, high-density ASIC packages and optimize package pinouts with system-level trade-offs, using Cadence APD or SiP tool suites.

The role includes substrate breakout patterns, routing, placement, and CAD library development to improve productivity. The ideal candidate has a BS in Electrical Engineering or equivalent experience, 5+ years in PCB layout, and strong SI knowledge.

Qualifications

• Must have a B.S. in Electrical Engineering or equivalent experience.
• Minimum 5+ years of PCB layout experience in graphics cards, motherboards, line cards or related tech.
• Proven substrate layout experience for wire bond and flip chip packages preferred.
• Strong background with Cadence APD or SiP and/or PCB layout tools including Constraint Manager.
• Solid understanding of high-speed design signal integrity practices.
• Experience with Virtuoso and Calibre is a plus; Valor experience is helpful.

Responsibilities

• Collaborate in a Layout team to implement high speed/density ASIC packages.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pinout considering system-level trade-offs.
• Support package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.
• Propose layout design trade-offs to the Technical Package Lead for decisions.
• Conduct design feasibility studies for size, cost, and performance goals.
• Develop symbols and CAD library databases using Cadence APD design tools.
• Develop methodologies to improve layout productivity.

Education

B.S. Electrical Engineering or equivalent experience

5+ years PCB Layout experience

Tools

Cadence APD or SiP

PCB layout tools (Constraint Manager)

Virtuoso

Calibre

Valor

Job description

NVIDIA is seeking a Senior Package Layout Engineer in California to join the Layout team. You will implement high-speed, high-density ASIC packages and optimize package pinouts with system-level trade-offs, using Cadence APD or SiP tool suites.

The role includes substrate breakout patterns, routing, placement, and CAD library development to improve productivity. The ideal candidate has a BS in Electrical Engineering or equivalent experience, 5+ years in PCB layout, and strong SI knowledge.