Senior Package Layout Engineer - Hardware

2100 NVIDIA USA; Santa Clara (CA); On-site; USD 136,000 - 258,750; Full time

Job summary

NVIDIA Corporation in Santa Clara, California is looking for a Senior Package Layout Engineer to lead the design of detailed layouts for IC substrates. You will collaborate with design teams to resolve issues and optimize high-speed ASIC packages.

The ideal candidate has over 5 years of experience in PCB layout on technologies like graphics cards and motherboards, with a strong background in tools like Cadence APD. This role offers competitive compensation and equity benefits.

Qualifications

• 5+ years of PCB layout experience on graphics cards, motherboards, or related technology.
• Experience with HDI designs is a plus.
• Proven experience in substrate layout of wire-bond and flip-chip packages.

Responsibilities

• Collaborate with design teams to develop detailed IC substrate layouts.
• Plan schedules and resolve design issues with teams.
• Perform substrate breakout patterns for ASIC packages.

Skills

PCB layout experience on graphics cards, motherboards

High-density interconnect (HDI) designs

Cadence APD or SiP tools

Signal integrity practices

Education

B.S. in Electrical Engineering or equivalent experience

Tools

Cadence APD

Valor

Virtuoso

Calibre

Job description

Overview

NVIDIA's GPUs and SOCs are the world leaders in power, performance, and efficiency. We continually innovate to deliver new and creative, unusual solutions to extraordinary problems across a wide range of sectors. This Senior Package Layout Engineer will play a key role in developing sophisticated, detailed layout of IC substrates for NVIDIA products.

Key Responsibilities

• Collaborate with the Technical Package Lead and design teams to design and develop detailed IC substrate layouts for NVIDIA products.
• Plan schedules and resolve cost, manufacturing, and electrical design issues with design teams.
• Implement high‑speed/density ASIC packages as part of the Layout team.
• Perform substrate breakout patterns for ASIC packages.
• Optimize package pin‑out, incorporating system‑level trade‑offs of pin assignment.
• Perform package routing, placement, stack‑up, reference plane, and power distribution using Cadence APD or SiP tool suite.
• Propose layout design trade‑offs to the Technical Package Lead for resolution and implementation.
• Conduct design feasibility studies to evaluate package design goals for size, cost, and system performance.
• Develop symbols and CAD library databases using Cadence APD design tools.
• Develop methodologies to improve layout productivity.

Key Qualifications

• B.S. in Electrical Engineering or equivalent experience.
• 5+ years of PCB layout experience on graphics cards, motherboards, line cards, or related technology.
• Experience with HDI designs is a plus.
• Proven experience in substrate layout of wire‑bond and flip‑chip packages.
• Significant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager).
• Solid understanding of high‑speed design signal‑integrity practices.
• Experience with Virtuoso and Calibre is a plus.
• Experience using Valor is helpful.

Compensation & Benefits

The base salary will be determined based on location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD – 212,750 USD for Level3 and 168,000 USD – 258,750 USD for Level4. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering an inclusive work environment and is an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.