Senior PCB Layout Engineer – High‑Speed, High‑Density | Equity Options

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 168,000 - 322,000; Full time

Benefits offered by this job

Equity eligibility

Competitive salary

Job summary

NVIDIA seeks an experienced Senior PCB Design Layout Engineer to join the Hardware Layout team in Santa Clara. You will design high‑speed, high‑density PCBs across NVIDIA units, from placement to pin-out, ensuring signal integrity and power distribution.

You will lead cross‑functional collaboration, manage complex projects, and produce complete documentation while meeting EMI/EMC and regulatory standards. This role demands strong problem‑solving in a fast‑paced environment.

Qualifications

• Leadership with track record of managing teams and projects.
• Strong communication and interpersonal skills for cross‑functional collaboration.
• Detail‑oriented with focus on quality and reliability in PCB layout.
• Adaptive to fast-paced, dynamic environments and changing priorities.

Responsibilities

• Collaborate with product design engineers to perform PCB layout for multiple units.
• Develop CAD layouts from placement to final pin-out ensuring topology and SI integrity.
• Produce release art-work files, ODB++, test reports and PCB documentation.
• Ensure designs meet SI constraints, EMI/RFI control and regulatory IPC specs.

Skills

Leadership

Cross-functional collaboration

Communication

Quality & reliability

Education

B.Sc. in Electrical Engineering

Advanced degree preferred

Tools

Cadence Allegro

Mentor Graphics

Job description

NVIDIA seeks an experienced Senior PCB Design Layout Engineer to join the Hardware Layout team in Santa Clara. You will design high‑speed, high‑density PCBs across NVIDIA units, from placement to pin-out, ensuring signal integrity and power distribution.

You will lead cross‑functional collaboration, manage complex projects, and produce complete documentation while meeting EMI/EMC and regulatory standards. This role demands strong problem‑solving in a fast‑paced environment.